CTNF 18/914,694 CTNF 100074 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement submitted on 14 Oct 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-2, 4-5, & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20080116862 A1) in view of Byrne (US 5828205 A) . Regarding Claim 1 , Yang teaches a voltage regulator (see Fig 3) comprising: a first control loop to generate a first control signal for a first pass transistor (31 is in a control loop with 33 to generate its control signal, Fig 3) , a second pass transistor (32, Fig 3) , and coupled between a supply voltage node and a regulated voltage node (32 is between Vin and Vo, Fig 3) ; a second control loop to generate a second control signal for the second pass transistor (error amplifier 34 is in the control loop of 32, Fig 3) ; and a voltage divider circuit coupled between the regulated voltage node and a ground node to provide a first feedback voltage from a first tap of the voltage divider circuit to the first control loop and to provide a second feedback voltage from a second tap of the voltage divider circuit to the second control loop (voltage divider 35 is connected between Vo and ground and has a first tap connected to 33 and a second tap connected to 34, Fig 3) . Yang does not teach the first control signal coupled to an output terminal of an integrated circuit, a second pass transistor internal to the integrated circuit. Byrne teaches a conventional voltage regulator circuit (see Fig 1) including the first control signal coupled to an output terminal of an integrated circuit (external pass transistor 25's gate is connected to output terminal 19 of IC 12, Fig 1, Col 2[36-8]) , a second pass transistor (15, Fig 1) internal to the integrated circuit ("Integrated Circuit (IC 12) mounted on a chip 10 and the integrated circuit includes a voltage regulator circuit 20 having an internal pass transistor 15.", Fig 1, Col 2[6-9]) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the known technique of using Byrne's external pass transistor with on-chip control to improve Yang's voltage regulator circuit, as it provides the advantage of decreasing power/heat dissipation on the IC (Col 1[56-9], of Byrne) . Regarding Claim 2 , the combination of Yang and Byrne discloses all of the limitations of Claim 1 above, and further discloses further comprising the first pass transistor external to the integrated circuit (external pass transistor 25's gate is connected to output terminal 19 of IC 12, Fig 1, Col 2[36-8] of Byrne) , the first pass transistor being coupled to the first control signal through the output terminal of the integrated circuit (external pass transistor 25's gate is connected to output terminal 19 of IC 12, Fig 1, Col 2[36-8] of Byrne) , the first pass transistor coupled between the supply voltage node and the regulated voltage node (external pass transistor 25 is connected between Vsupply and the output of IC 12 that goes to the load 31, Fig 1 of Byrne) . Regarding Claim 4 , the combination of Yang and Byrne discloses all of the limitations of Claim 1 above, and further discloses wherein the first control loop comprises a first error amplifier having a first input coupled to the first feedback voltage and a second input coupled to a reference voltage, the first error amplifier supplying the first control signal (error amplifier 33 receives Vfb2 on its negative input from 35 and receives Vref on its positive input and its output controls 31, Fig 3 of Yang) . Regarding Claim 5 , the combination of Yang and Byrne discloses all of the limitations of Claim 4 above, and further discloses wherein the second control loop comprises a second error amplifier having a first input coupled to the second feedback voltage and having a second input coupled to the reference voltage, the second error amplifier generating the second control signal that is coupled to a control terminal of the second pass transistor (error amplifier 34 receives Vfb1 on its positive input from 35 and receives Vref on its negative input and its output controls 32, Fig 3 of Yang) . Regarding Claim 8 , the combination of Yang and Byrne discloses all of the limitations of Claim 5 above, and further discloses wherein the second error amplifier is responsive to a first value of an internal ballast enable signal to turn on and to a second value of the internal ballast enable signal to turn off and thereby disable the second pass transistor (voltage detection circuit 50 can disable/enable 34/32 via its signal ENB being high or low, Fig 3 of Yang) . The combination of Yang and Byrne does not disclose wherein the first error amplifier is responsive to a first value of an external ballast enable signal to turn on and to a second value of the external ballast enable signal to turn off to thereby disable the first pass transistor. The courts have long found that mere duplication of parts is an obviousness type consideration. See MPEP 2144.04 VI. and In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Thus, before the earliest effective filling date it would have been obvious to configure Yang with wherein the first error amplifier is responsive to a first value of an external ballast enable signal to turn on and to a second value of the external ballast enable signal to turn off to thereby disable the first pass transistor (by using a second voltage detection circuit 50 that can disable/enable 33/31 via its signal ENB being high or low, Fig 3 of Yang) . The reason for doing so would have been to provide overcurrent protection in the event of a fault . 07-21-aia AIA Claim s 3, 6, 10, 12, & 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20080116862 A1) in view of Byrne (US 5828205 A), and further in view of Xi (US 20030178976 A1) . Regarding Claim 3 , the combination of Yang and Byrne discloses all of the limitations of Claim 1 above. The combination of Yang and Byrne does not disclose wherein the first control loop has a higher priority than the second control loop to thereby reduce an amount of current supplied by the second pass transistor. Xi teaches a conventional LDO with concurrently operating feedback loops (see Fig 2) including wherein the first control loop has a higher priority than the second control loop to thereby reduce an amount of current supplied by the second pass transistor ("Once the input voltage has dropped by an amount of the voltage DeltV, amplifier 228 will start decreasing voltage on line 230 to drive the voltage on the gate of PMOS transistor 256 away from the voltage on line 202 in order to turn on transistor 256 to regulate the output voltage at node 260.", Fig 2, [0019]) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the LDO in Yang, as taught by Xi, as it provides the advantage of concurrently operating two pass transistors for smoother startup and transition behavior. Regarding Claim 6 , the combination of Yang and Byrne discloses all of the limitations of Claim 5 above, and further discloses the second control loop can be disabled (50 can disable 34/32 after Vin reaches a threshold which would be after startup, Fig 3 of Yang) . The combination of Yang and Byrne does not disclose wherein during a startup sequence, by default the first control loop and the second control loop run concurrently and the first control loop is prioritized to ensure the first pass transistor provides more current than the second pass transistor at an end of the startup sequence and after the startup sequence completes the first control loop can be disabled. The courts have long found that mere duplication of parts is an obviousness type consideration. See MPEP 2144.04 VI. and In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Thus, before the earliest effective filling date it would have been obvious to configure Yang with after the startup sequence completes the first control loop can be disabled (by using a second voltage detection circuit 50 that can disable 33/31 after Vin reaches a threshold which would be after startup, Fig 3 of Yang) . The reason for doing so would have been to provide overcurrent protection in the event of a fault. Xi teaches a conventional LDO with concurrently operating feedback loops (see Fig 2) including wherein during a startup sequence (transition from SLEEP to ON mode, Fig 2, [0019] of Xi) , by default the first control loop and the second control loop run concurrently (250 and 256 regulate the load current, Fig 2, [0019] of Xi) and the first control loop is prioritized to ensure the first pass transistor provides more current than the second pass transistor at an end of the startup sequence (256 handles more of the load current, Fig 2, [0019] of Xi) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the LDO in Yang, as taught by Xi, as it provides the advantage of concurrently operating two pass transistors for smoother startup and transition behavior. Regarding Claim 10 , Yang teaches method for generating a regulated voltage (see Fig 3) comprising: controlling a first pass transistor (31, Fig 3) , using a first control loop (31 is in a control loop with 33 to generate its control signal, Fig 3) ; controlling a second pass transistor (32, Fig 3) , using a second control loop (error amplifier 34 is in the control loop of 32, Fig 3) , supplying a first feedback voltage from a first tap of a voltage divider circuit to the first control loop (Vfb2 from voltage divider 35 connects to 33 to control 31, Fig 3) ; and supplying a second feedback voltage from a second tap of the voltage divider circuit to the second control loop (Vfb1 from voltage divider 35 connects to 34 to control 32, Fig 3) . Yang does not teach a first pass transistor that is external to an integrated circuit, integrated circuit, a second control loop that runs concurrently with the first control loop, a second control loop that runs concurrently with the first control loop. Byrne teaches a conventional voltage regulator circuit (see Fig 1) including the controlling a first pass transistor that is external to an integrated circuit (external pass transistor 25's gate is connected to output terminal 19 of IC 12, Fig 1, Col 2[36-8]) , controlling a second pass transistor that is internal to the integrated circuit ("Integrated Circuit (IC 12) mounted on a chip 10 and the integrated circuit includes a voltage regulator circuit 20 having an internal pass transistor 15.", Fig 1, Col 2[6-9]) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the known technique of using Byrne's external pass transistor with on-chip control to improve Yang's voltage regulator circuit, as it provides the advantage of decreasing power/heat dissipation on the IC (Col 1[56-9], of Byrne) . Xi teaches a conventional LDO with concurrently operating feedback loops (see Fig 2) including a second control loop that runs concurrently with the first control loop (first loop with amplifier 216 and pass transistor 250 runs concurrently with the second loop containing amplifier 228 and pass transistor 256, Fig 2, [0019]) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the LDO with concurrently operating feedback loops in Yang, as taught by Xi, as it provides the advantage of concurrently operating two pass transistors for smoother startup and transition behavior. Regarding Claim 12 , the combination of Yang, Byrne, and Xi discloses all of the limitations of Claim 10 above, and further discloses further comprising: supplying the first feedback voltage to a first input of a first error amplifier in the first control loop (error amplifier 33 receives Vfb2 on its negative input from 35, Fig 3 of Yang) ; supplying a reference voltage to a second input of the first error amplifier (Vref is on the positive input of 33, Fig 3 of Yang) ; and supplying an error output signal of the first error amplifier to a control terminal of the first pass transistor to control the first pass transistor (the output of error amplifier 33 controls 31, Fig 3 of Yang) . Regarding Claim 14 , the combination of Yang, Byrne, and Xi discloses all of the limitations of Claim 12 above. The combination of Yang, Byrne, and Xi does not disclose further comprising turning on the first error amplifier responsive to a first value of an external ballast enable signal and turning off the first error amplifier responsive to a second value of the external ballast enable signal to thereby disable the first pass transistor. The courts have long found that mere duplication of parts is an obviousness type consideration. See MPEP 2144.04 VI. and In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Thus before the earliest effective filling date it would have been obvious to configure Yang with further comprising turning on the first error amplifier responsive to a first value of an external ballast enable signal and turning off the first error amplifier responsive to a second value of the external ballast enable signal to thereby disable the first pass transistor (by using a second voltage detection circuit 50 that can enable/disable 33/31 via the ENB signal being high or low, Fig 3 of Yang) . The reason for doing so would have been to provide overcurrent protection in the event of a fault. Regarding Claim 15 , the combination of Yang, Byrne, and Xi discloses all of the limitations of Claim 10 above, and further discloses further comprising: supplying the second feedback voltage to a first input of a second error amplifier in the second control loop (error amplifier 34 receives Vfb1 on its positive input from 35, Fig 3 of Yang) ; supplying a reference voltage to a second input of the second error amplifier (Vref is on the negative input of 34, Fig 3 of Yang) ; and supplying an error output signal of the second error amplifier to a control terminal of the second pass transistor to control the second pass transistor (the output of error amplifier 34 controls 32, Fig 3 of Yang) . Regarding Claim 16 , the combination of Yang, Byrne, and Xi discloses all of the limitations of Claim 15 above, and further discloses further comprising prioritizing the first control loop by default during a startup sequence (first loop with amplifier 216 and pass transistor 250 dominates in the transition from SLEEP mode to ON mode since 250 is already on in SLEEP mode and then 256 is gradually turned on, Fig 2, [0019] of Xi) . Regarding Claim 17 , the combination of Yang, Byrne, and Xi discloses all of the limitations of Claim 16 above, and further discloses further comprising disabling the first control loop or the second control loop after the startup sequence completes (50 disables 32 when Vin is above a threshold which occurs after Vin has risen and regulation is established, Fig 5 of Yang) . Regarding Claim 18 , the combination of Yang, Byrne, and Xi discloses all of the limitations of Claim 15 above, and further discloses further comprising turning on the second error amplifier responsive to a first value of an internal ballast enable signal and turning off the second error amplifier responsive to a second value of the internal ballast enable signal to thereby disable the second pass transistor (50 sends enable/disable signal ENB to 34, Fig 5 of Yang) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 19-20 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 7, 9, 11, & 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.C.C./Examiner, Art Unit 2838 /GARY L LAXTON/Primary Examiner, Art Unit 2838 6/11/2026 Application/Control Number: 18/914,694 Page 2 Art Unit: 2838 Application/Control Number: 18/914,694 Page 3 Art Unit: 2838 Application/Control Number: 18/914,694 Page 4 Art Unit: 2838 Application/Control Number: 18/914,694 Page 5 Art Unit: 2838 Application/Control Number: 18/914,694 Page 6 Art Unit: 2838 Application/Control Number: 18/914,694 Page 7 Art Unit: 2838 Application/Control Number: 18/914,694 Page 8 Art Unit: 2838 Application/Control Number: 18/914,694 Page 9 Art Unit: 2838 Application/Control Number: 18/914,694 Page 10 Art Unit: 2838 Application/Control Number: 18/914,694 Page 11 Art Unit: 2838 Application/Control Number: 18/914,694 Page 12 Art Unit: 2838 Application/Control Number: 18/914,694 Page 13 Art Unit: 2838
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