DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/26/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka (US 2021/0034092) in view of Beggs (US 5621307) further in view of Yamamoto (US 2019/0115481).
Regarding claim 1, Tomioka discloses a characteristic compensation circuit [see fig. 7] comprising: a bias circuit [103]; a first embedded Zener diode [104] having a cathode [cathode 104] connected to a first node [node between 103 and 104], and an anode [anode 104] connected to a ground node [ground], the first embedded Zener diode [104] configured to be biased by the bias circuit in a direction from the cathode to the anode [a reverse direction, par. 0005]; a second embedded diode [105] having a cathode [cathode 105] connected to the ground node, and an anode [anode 105] connected to a second node [node between 106 and 107], the second embedded diode [105] configured to be biased by the bias circuit in a direction from the anode to the cathode [a forward direction]; and a resistive divider [106 and 107] having a resistor [107] connected between the first node and the second node, the resistive divider configured to output an output voltage [Vout] based on the resistor [par. 0007], wherein the resistive divider is configured to compensate for a temperature characteristic [par. 0005-0015] of the output voltage by weighting and summing a first voltage [Vz] and a second voltage [Vd], the first voltage being a voltage applied to the first embedded Zener diode [Vz], the second voltage being a voltage applied to the second embedded diode [Vd]. Tomioka does not explicitly disclose a second Zener diode and each of the first embedded Zener diode and the second embedded Zener diode has a junction located deeper than a surface of a semiconductor wafer in which the first embedded Zener diode and the second embedded Zener diode are formed..
In the same field of endeavor, Beggs discloses a forward biased Zener diodes [e.g. D2, D4, fig. 1]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka by incorporating Zener diode operating in a forward bias in place of standard diode [105 of Tomioka fig. 7], because such an obvious modification would have been the mere substitution of known art recognized alternative Zener diode routinely chosen as necessary by those of ordinary skill in the art as taught in Beggs in order to provide a negative temperature coefficient compensation circuit [abstract]. Tomioka in view of Beggs does not explicitly disclose each of the first embedded Zener diode and the second embedded Zener diode has a junction located deeper than a surface of a semiconductor wafer in which the first embedded Zener diode and the second embedded Zener diode are formed.
However, Yamamoto discloses a diode [AD1-AD2, fig. 13] has a junction [A11] located deeper than a surface [top surface A21] of a semiconductor wafer [A2] in which the first embedded Zener diode and the second embedded Zener diode are formed. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka in view of Beggs by incorporating a junction located deeper than a surface as taught in Yamamoto in order to provide an improved technique for increasing the junction depth, the electric performance of the chip is improved well, the package can be manufactured as a device of high reliability.
Regarding claim 2, Tomioka in view of Beggs further in view of Yamamoto discloses [fig. 7] wherein the resistive divider includes resistors [107 and 106] connected in series, and the resistive divider is configured to output [Vout], as the output voltage, a divided voltage based on the resistors [par. 0007].
Regarding claim 8, Tomioka in view of Beggs further in view of Yamamoto discloses [fig. 7] wherein the bias circuit includes a current source [current source 103] configured to generate a constant current [par. 0005] and continuously output the constant current to the first node, and a magnitude of the constant current supplied to the first node is independent of a temperature change [par. 0013].
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Beggs and Yamamoto further in view of Shu (US 2020/0271700).
Regarding claim 3, Tomioka in view of Beggs further in view of Yamamoto discloses all the features with respect to claim 1 as outlined above. Tomioka in view of Beggs further in view of Yamamoto further discloses [see fig. 7] wherein the resistive divider includes resistors [106/107] connected in series, common connection nodes [node between 106 and 107] between adjacent two of the resistors. Tomioka in view of Beggs further in view of Yamamoto does not explicitly disclose semiconductor switches connected in parallel to the resistors, the semiconductor switches including input terminals connected to the common connection nodes, respectively, and output terminals commonly connected, and the resistive divider is configured to output a divided voltage, which is acquired based on the resistors, through an input terminal and an output terminal of one of the semiconductor switches.
However, Shu discloses [see fig. 1] semiconductor switches [S1-S4, par. 0023] connected in parallel to resistors [R1-RN], the semiconductor switches including input terminals [terminals V1-V4] connected to common connection nodes [111-114], respectively, and output terminals commonly connected [commonly connected node at 108], and resistive divider [102] is configured to output a divided voltage [V1-V4], which is acquired based on the resistors, through an input terminal [input terminal V1 of S1] and an output terminal [output terminal of S1 connected to 108] of one of the semiconductor switches. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka in view of Beggs further in view of Yamamoto by incorporating semiconductor switches connected in parallel to resistors as taught in Shu in order utilize well known voltage divider.
Regarding claim 6, Tomioka in view of Beggs and Yamamoto further in view of Shu discloses [fig. 1] wherein each of the semiconductor switches [S1-S4] includes at least one metal-oxide-semiconductor transistor [par. 0023] having at least one control terminal, and each of the semiconductor switches is configured to switch between an open state [OFF] and a short state [ON] between an input terminal [input terminal V1 of S1] and an output terminal [output terminal of S1 connected to 108] based on a voltage [125] applied to the at least one control terminal [control S1/S2/S3/S4].
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Beggs and Yamamoto further in view of Marum et al. (US 5500546).
Regarding claims 4 and 5, Tomioka in view of Beggs further in view of Yamamoto discloses all the features with respect to claim 1 as outlined above. Tomioka in view of Beggs further in view of Yamamoto does not explicitly disclose wherein layout of the first embedded Zener diode is same as a layout of the second embedded Zener diode and wherein the first embedded Zener diode is located to be adjacent to the second embedded Zener diode.
However, Marum discloses [fig. 3b~3d] a layout of first embedded Zener diode is same as a layout of second embedded Zener diode and wherein the first embedded Zener diode is located to be adjacent to the second embedded Zener diode. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka in view of Beggs further in view of Yamamoto by incorporating the layout as taught in Marum in order to save die area and decreasing circuit cost [cl. 6, ln. 32-49].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Beggs and Yamamoto and Marum et al. further in view of Dabral et al. (US 7012304 and Debral hereinafter).
Regarding claim 7, Tomioka in view of Beggs and Yamamoto further in view of Marum discloses all the features with respect to claim 4 as outlined above. Tomioka in view of Beggs and Yamamoto further in view of Marum does not explicitly disclose wherein the first embedded Zener diode is formed in a first formation area, the second embedded Zener diode is formed in a second formation area different from the first formation area, and the first formation area and the second formation area are mutually non-overlapping in a plan view and disposed adjacent to each other.
However, Debral discloses [fig. 10b] first embedded Zener diode [diode in 195] is formed in a first formation area [1951], the second embedded Zener diode [diode in 1952] is formed in a second formation area [1952] different from the first formation area, and the first formation area and the second formation area are mutually non-overlapping in a plan view and disposed adjacent to each other. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka /Beggs and Yamamoto /Marum by incorporating the layout as taught in Debral in order to enhance the diodes performance [cl. 7, ln. 42-53].
Response to Arguments
Applicant’s arguments filed on 08/26/2026 with respect to claim 1 have been considered but are moot because the new ground of rejection.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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