DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed in claim 1, lines 15-16 “a junction located deeper than a surface of a semiconductor wafer must” be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “each of the first embedded Zener diode and the second embedded Zener diode has a junction located deeper than a surface of a semiconductor wafer”. It is unclear what “surface” applicant refers.
Claim 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka (US 2021/0034092) in view of Beggs (US 5621307) further in view of Liu et al. (CN 220138323 U and Liu hereinafter).
Regarding claim 1, Tomioka discloses a characteristic compensation circuit [see fig. 7] comprising: a bias circuit [103]; a first embedded Zener diode [104] having a cathode [cathode 104] connected to a first node [node between 103 and 104], and an anode [anode 104] connected to a ground node [ground], the first embedded Zener diode [104] configured to be biased by the bias circuit in a direction from the cathode to the anode [a reverse direction, par. 0005]; a second embedded diode [105] having a cathode [cathode 105] connected to the ground node, and an anode [anode 105] connected to a second node [node between 106 and 107], the second embedded diode [105] configured to be biased by the bias circuit in a direction from the anode to the cathode [a forward direction]; and a resistive divider [106 and 107] having a resistor [107] connected between the first node and the second node, the resistive divider configured to output an output voltage [Vout] based on the resistor [par. 0007], wherein the resistive divider is configured to compensate for a temperature characteristic [par. 0005-0015] of the output voltage by weighting and summing a first voltage [Vz] and a second voltage [Vd], the first voltage being a voltage applied to the first embedded Zener diode [Vz], the second voltage being a voltage applied to the second embedded diode [Vd]. Tomioka does not explicitly disclose a second Zener diode and each of the first embedded Zener diode and the second embedded Zener diode has a junction located deeper than a surface of a semiconductor wafer.
In the same field of endeavor, Beggs discloses a forward biased Zener diodes [e.g. D2, D4, fig. 1]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka by incorporating Zener diode operating in a forward bias in place of standard diode [105 of Tomioka fig. 7], because such an obvious modification would have been the mere substitution of known art recognized alternative Zener diode routinely chosen as necessary by those of ordinary skill in the art as taught in Beggs in order to provide a negative temperature coefficient compensation circuit [abstract]. Tomioka in view of Beggs does not explicitly disclose each of the first embedded Zener diode and the second embedded Zener diode has a junction located deeper than a surface of a semiconductor wafer.
However, Liu discloses a diode [fig. 2] has a junction [PN junction 30] located deeper than a surface [50] of a semiconductor wafer [fig. 2]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka in view of Beggs by incorporating a junction located deeper than a surface as taught in Liu in order to provide an improved technique for increasing the junction depth, the electric performance of the chip is improved well, especially the VF at high temperature is greatly reduced, so the diode can pass the temperature rise test.
Regarding claim 2, Tomioka in view of Beggs further in view of Liu discloses [fig. 7] wherein the resistive divider includes resistors [107 and 106] connected in series, and the resistive divider is configured to output [Vout], as the output voltage, a divided voltage based on the resistors [par. 0007].
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Beggs and Liu further in view of Shu (US 2020/0271700).
Regarding claim 3, Tomioka in view of Beggs further in view of Liu discloses all the features with respect to claim 1 as outlined above. Tomioka in view of Beggs further in view of Liu further discloses [see fig. 7] wherein the resistive divider includes resistors [106/107] connected in series, common connection nodes [node between 106 and 107] between adjacent two of the resistors. Tomioka in view of Beggs further in view of Liu does not explicitly disclose semiconductor switches connected in parallel to the resistors, the semiconductor switches including input terminals connected to the common connection nodes, respectively, and output terminals commonly connected, and the resistive divider is configured to output a divided voltage, which is acquired based on the resistors, through an input terminal and an output terminal of one of the semiconductor switches.
However, Shu discloses [see fig. 1] semiconductor switches [S1-S4, par. 0023] connected in parallel to resistors [R1-RN], the semiconductor switches including input terminals [terminals V1-V4] connected to common connection nodes [111-114], respectively, and output terminals commonly connected [commonly connected node at 108], and resistive divider [102] is configured to output a divided voltage [V1-V4], which is acquired based on the resistors, through an input terminal [input terminal V1 of S1] and an output terminal [output terminal of S1 connected to 108] of one of the semiconductor switches. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka in view of Beggs further in view of Liu by incorporating semiconductor switches connected in parallel to resistors as taught in Shu in order utilize well known voltage divider.
Regarding claim 6, Tomioka in view of Beggs further in view of Liu further in view of Shu discloses [fig. 1] wherein each of the semiconductor switches [S1-S4] includes at least one metal-oxide-semiconductor transistor [par. 0023] having at least one control terminal, and each of the semiconductor switches is configured to switch between an open state [OFF] and a short state [ON] between an input terminal [input terminal V1 of S1] and an output terminal [output terminal of S1 connected to 108] based on a voltage [125] applied to the at least one control terminal [control S1/S2/S3/S4].
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Beggs and Liu further in view of Marum et al. (US 5500546).
Regarding claims 4 and 5, Tomioka in view of Beggs further in view of Liu discloses all the features with respect to claim 1 as outlined above. Tomioka in view of Beggs further in view of Liu does not explicitly disclose wherein a layout of the first embedded Zener diode is same as a layout of the second embedded Zener diode and wherein the first embedded Zener diode is located to be adjacent to the second embedded Zener diode.
However, Marum discloses [fig. 3b~3d] a layout of first embedded Zener diode is same as a layout of second embedded Zener diode and wherein the first embedded Zener diode is located to be adjacent to the second embedded Zener diode. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka in view of Beggs further in view of Liu by incorporating the layout as taught in Marum in order to save die area and decreasing circuit cost [cl. 6, ln. 32-49].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tomioka in view of Beggs and Liu and Marum et al. further in view of Dabral et al. (US 7012304 and Debral hereinafter).
Regarding claim 7, Tomioka in view of Beggs and Liu further in view of Marum discloses all the features with respect to claim 4 as outlined above. Tomioka in view of Beggs and Liu further in view of Marum does not explicitly disclose wherein the first embedded Zener diode is formed in a first formation area, the second embedded Zener diode is formed in a second formation area different from the first formation area, and the first formation area and the second formation area are mutually non-overlapping in a plan view and disposed adjacent to each other.
However, Debral discloses [fig. 10b] first embedded Zener diode [diode in 195] is formed in a first formation area [1951], the second embedded Zener diode [diode in 1952] is formed in a second formation area [1952] different from the first formation area, and the first formation area and the second formation area are mutually non-overlapping in a plan view and disposed adjacent to each other. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Tomioka /Beggs and Liu /Marum by incorporating the layout as taught in Debral in order to enhace the diodes performance [cl. 7, ln. 42-53].
Response to Arguments
Applicant’s arguments filed on 03/13/2026 with respect to claim 1 have been considered but are moot because the new ground of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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