DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 30 March 2026 is entered.
Response to Arguments
Applicant’s arguments have been fully considered but they are not persuasive.
i. Applicant’s arguments directed toward the failure of cited prior art to disclose the claimed matching of voltage domains is moot in view of the new reference Cho et al. (2024/0203977), which will not be discussed here, for brevity.
ii. Additional arguments directed toward the failure of additionally cited prior art to cure above argued deficiencies are moot in view of the new grounds of rejection, indicated above.
Claim Objections
Prior objection to claims’ recitation of informalities is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 1 – 7, 9, 10, 12, 20, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Fujikawa (2021/0110747) and Liu et al. (2022/0180784; hereinafter Liu) in view of Cho et al. (2024/0203977; hereinafter Cho; this combination of references hereinafter referred to as FLC).
Regarding claim 1, Fujikawa discloses a display panel (Figure 1: Comprising 2), comprising:
a plurality of first signal lines (Comprising 14);
a plurality of power signal lines (Comprising 19, 21, 23, 24); and
a plurality of electrostatic discharge circuits (Comprising 17a, 17b), wherein
the plurality of electrostatic discharge circuits includes a first electrostatic discharge circuit (Comprising 17a) and a second electrostatic discharge circuit (Comprising 17b);
the first electrostatic discharge circuit (Comprising 17a) includes a first terminal (Electrically connected with 13) and a second terminal (Electrically connected with 19a), and
the second electrostatic discharge circuit (Comprising 17b) includes a first terminal (Electrically connected with 13) and a second terminal (Electrically connected with 21a);
the first terminals of the first electrostatic discharge circuit (Each among 17a electrically connected to respective instances of 13) and the second electrostatic discharge circuit (Each among 17b electrically connected to respective instances of 13) are electrically connected to different first signal lines respectively (Corresponding to 14a, 14b); and
the second terminals of the first electrostatic discharge circuit (Each among 17a electrically connected to at least one of 19a, 23a) and the second electrostatic discharge circuit (Each among 17b electrically connected to at least one of 21a, 24a) are electrically connected to different power signal lines respectively (Corresponding to one of the groups of 19 and 23, or 21 and 24), wherein
the plurality of electrostatic discharge circuits (Comprising 17a, 17b) is arranged along a first direction (Comprising +X, –X), and
the plurality of power signal lines (Comprising 19, 21, 23, 24) extend along the first direction (Comprising +X, –X) and
power signal lines (Comprising 19, 21, 23, 24) connected to the plurality of electrostatic discharge circuits (Comprising 17a, 17b) are disposed on sides of the plurality of electrostatic discharge circuits (Comprising 17a, 17b) along a second direction (Comprising +Y, –Y), and
the first direction (Comprising +X, –X) is perpendicular to the second direction (Comprising +Y, –Y).
Fujikawa does not explicitly disclose the panel wherein power signal lines are disposed on a same side of the plurality of electrostatic discharge circuits.
In the same field of endeavor, Liu teaches a display [0002] wherein power signal lines (Figure 6: Comprising VGL, VGH) are disposed on a same side of the plurality of electrostatic discharge circuits (Comprising ESDi1), an alternative to the configuration of power signal lines being formed on both sides of the electrostatic discharge circuits (Figure 10) each accommodating a respective one of device wiring schemes [0079]. The teaching by Liu of both power signal line configurations establishes that an Artisan would have been motivated to reconfigure the power signal lines positioning of Fujikawa in view of the teaching of Liu, with a reasonable expectation of success.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified wherein power signal lines are disposed on a same side of the plurality of electrostatic discharge circuits, in view of the teaching of Liu, in view of the reasoning above.
Fujikawa in view of Liu does not explicitly disclose the panel wherein a first power signal line connected to the first electrostatic discharge circuit has a voltage domain that matches a voltage domain of a first signal line connected to the first electrostatic discharge circuit, and a second power signal line connected to the second electrostatic discharge circuit has a voltage domain that matches a voltage domain of a second signal line connected to the second electrostatic discharge circuit.
In the same field of endeavor, Cho discloses a semiconductor device [0002] with electrostatic discharge protection included among interface cells [0042] disposed in the same power domain of a logic cell [0110]. The driver circuit (Figure 9: Comprising 530) is one the same voltage rails (Comprising VDD, VSS) as the ESD diode (Comprising 520). Driving circuitry may be powered with the same domain of voltage values applied to its corresponding electrostatic discharge protection circuitry. This is among measures implemented to reduce a routing path [0147] and preserve a uniform device thickness [0133].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified wherein a first power signal line connected to the first electrostatic discharge circuit has a voltage domain that matches a voltage domain of a first signal line connected to the first electrostatic discharge circuit, and a second power signal line connected to the second electrostatic discharge circuit has a voltage domain that matches a voltage domain of a second signal line connected to the second electrostatic discharge circuit, in view of the teaching of Cho, to preserve uniform device thickness.
Regarding claim 2, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel wherein: the first terminals (Electrically connected with 13) of the first electrostatic discharge circuit (Comprising 17a) and the second electrostatic discharge circuit (Comprising 17b) are electrostatic input terminals ([0142]: Static electricity entering from 13); the second terminals of the first electrostatic discharge circuit and the second electrostatic discharge circuit are electrostatic output terminals ([0118]: Through which resulting current passes; example of 19b); and a quantity of the electrostatic output terminals is at least two (See also, 21b, 23b [0080], 24b [0090]).
Regarding claim 3, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel wherein: the plurality of power signal lines include a first group of power signal lines (Comprising 19, 23) and a second group of power signal lines (Comprising 21, 24); and the first group of power signal lines includes a first power signal line and a second power signal line (Comprising 19, 23); and the second group of power signal lines includes a first power signal line and a second power signal line (Comprising 21, 24); a power signal voltage of the first power signal line in the first group of power signal lines is V11 ([0074]: V19), and a power signal voltage of the second power signal line in the first group of power signal lines is V12 ([0074]: V23); and a power signal voltage of the first power signal line in the second group of power signal lines is V21 ([0074]: V21), and a power signal voltage of the second power signal line in the second group of power signal lines is V22 ([0074]: V24), wherein V11>V12 ([0075]: V19{14.5V}>V23{10.5V}), V21>V22 ([0075]: V21{5.5V}>V24{1V}), V11≠V21 ([0075]: V19{14.5V}≠V21{5.5V}), and V12≠V22 ([0075]: V23{10.5V}≠V24{1V}); and two second terminals of the first electrostatic discharge circuit (Each of 19a and 23a, electrically connected to 17a) are electrically connected to the first power signal line and the second power signal line in the first group of power signal lines respectively (Comprising 19, 23); and two second terminals of the second electrostatic discharge circuit (Each of 21a and 24a, electrically connected to 17b) are electrically connected to the first power signal line and the second power signal line in the second group of power signal lines respectively (Comprising 21, 24).
Regarding claim 4, FLC discloses the display panel according to claim 3. Fujikawa discloses the panel wherein: (V11-V21) × (V12-V22) > 0 ([0075]: {14.5V – 5.5V = 9V} x {10.5V – 1V = 9.5V} = 85.5V).
Regarding claim 5, FLC discloses the display panel according to claim 3. Fujikawa discloses the panel wherein: V11-V21 ≈ V12-V22 ([0075]: {14.5V – 5.5V = 9V} ≈ {10.5V – 1V = 9.5V}).
Fujikawa does not expressly state the panel being provided wherein V11-V21 = V12-V22.
However, it would have been an obvious design choice to one having ordinary skill in the art to set the above indicated voltage differences equal to one another, as claimed, as Applicant has not disclosed the equated differences providing an advantage, being used for a particular purpose or solving a stated problem. One having ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with the 0.5 Volt offset of the differences, taught by Fujikawa, as implemented electrostatic discharge protection is in no way hindered thereby.
Therefore, it would have been an obvious matter of design choice to modify Fujikawa, to arrive at the claimed invention.
Regarding claim 6, FLC discloses the display panel according to claim 3. Fujikawa discloses the panel wherein: V11-V12 ≈ V21-V22 ([0075]: {14.5V – 10.5V = 4V}≈{5.5V – 1V = 4.5}).
Fujikawa does not expressly state the panel being provided wherein V11-V12 = V21-V22.
However, it would have been an obvious design choice to one having ordinary skill in the art to set the above indicated voltage differences equal to one another, as claimed, as Applicant has not disclosed the equated differences providing an advantage, being used for a particular purpose or solving a stated problem. One having ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with the 0.5 Volt offset of the differences, taught by Fujikawa, as implemented electrostatic discharge protection is in no way hindered thereby.
Therefore, it would have been an obvious matter of design choice to modify Fujikawa, to arrive at the claimed invention.
Regarding claim 7, FLC discloses the display panel according to claim 3. Fujikawa discloses the panel (Figure 1) wherein: the first electrostatic discharge circuit (Comprising 17a) includes a first transistor (Comprising 26) and a second transistor (Comprising 25); a control terminal and a first terminal of the first transistor (Comprising gate and one of source, drain electrodes of 26) are both electrically connected to the first power signal line in the first group of power signal lines (Comprising 23); a second terminal of the first transistor (Comprising other one of source, drain electrodes of 26) is electrically connected to a control terminal and a first terminal of the second transistor respectively (Comprising gate and one of source, drain electrodes of 25), and is configured as the first terminal of the first electrostatic discharge circuit (At which 17a is electrically connected to 13) to be electrically connected to a first signal line (Comprising 14a); and a second terminal of the second transistor (Comprising other one of source, drain of 25) is electrically connected to the second power signal line in the first group of power signal lines (Comprising 19); and the second electrostatic discharge circuit (Comprising 17b) includes a third transistor (Comprising 28) and a fourth transistor (Comprising 27); a control terminal and a first terminal of the third transistor (Comprising gate and one of source, drain electrodes of 28) are both electrically connected to the first power signal line in the second group of power signal lines (Comprising 24); a second terminal of the third transistor (Comprising other one of source, drain electrodes of 28) is electrically connected to a control terminal and a first terminal of the fourth transistor respectively (Comprising gate and one of source, drain electrodes of 27), and is configured as the first terminal of the second electrostatic discharge circuit (At which 17b is electrically connected to 13) to be electrically connected to a first signal line (Comprising 14b); and a second terminal of the fourth transistor (Comprising other one of source, drain of 27) is electrically connected to the second power signal line in the second group of power signal lines (Comprising 21).
Regarding claim 9, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel (Figure 1) wherein: along the second direction (Comprising +Y, –Y), the plurality of power signal lines (Comprising 19, 21, 23, 24) are on a side of the plurality of electrostatic discharge circuits (Comprising one of 17a, 17b) adjacent to or away from a first edge of the display panel (Comprising 2); and the first edge is an edge of the display panel (Comprising 2) closest to the electrostatic discharge circuit (Comprising one of 17a, 17b).
Regarding claim 10, FLC discloses the display panel according to claim 9. Fujikawa discloses the panel (Figure 1) wherein: along the second direction (Comprising +Y, –Y), the plurality of power signal lines (Comprising 19, 21, 23, 23) are on the side of the electrostatic discharge circuit (Comprising one of 17a, 17b) away from the first edge of the display panel (Comprising 2).
Regarding claim 12, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel (Figure 1) wherein: along the first direction (Comprising +X, –X), two first electrostatic discharge circuits are adjacent to each other (Among 17a); and first signal lines (Comprising 14a) connected to the two first electrostatic discharge circuits adjacent to each other (Among 17a) are respectively on two opposite sides (Instance of 14a in the +X direction relative to instance of 17a positioned further in –X direction; instance of 14a in the –X direction relative to instance of 17a positioned further in +X direction) of the two first electrostatic discharge circuits adjacent to each other (Among 17a); and along the first direction (Comprising +X, –X), two second electrostatic discharge circuits are adjacent to each other (Among 17b); and first signal lines (Comprising 14b) connected to the two second electrostatic discharge circuits adjacent to each other (Among 17b) are respectively on two opposite sides (Instance of 14b in the +X direction relative to instance of 17b positioned further in –X direction; instance of 14b in the –X direction relative to instance of 17b positioned further in +X direction) of the two second electrostatic discharge circuits adjacent to each other (Among 17b).
Regarding claim 20, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel (Figure 1) wherein: a signal range of a power signal line (Comprising 19, 23) electrically connected to the first electrostatic discharge circuit (Comprising 17a) is different from a signal range of a power signal line (Comprising 21, 24) electrically connected to the second electrostatic discharge circuit (Comprising 17b; [0075]: Difference [first high, first low] = 4 V; difference [second high, second low] = 4.5 V).
Regarding claim 23, Fujikawa discloses a display apparatus [0162], comprising:
a plurality of first signal lines (Figure 1: Comprising 14);
a plurality of power signal lines (Comprising 19, 21, 23, 24); and
a plurality of electrostatic discharge circuits (Comprising 17a, 17b), wherein
the plurality of electrostatic discharge circuits includes a first electrostatic discharge circuit (Comprising 17a) and a second electrostatic discharge circuit (Comprising 17b);
the first electrostatic discharge circuit (Comprising 17a) includes a first terminal (Electrically connected with 13) and a second terminal (Electrically connected with 19a), and
the second electrostatic discharge circuit (Comprising 17b) includes a first terminal (Electrically connected with 13) and a second terminal (Electrically connected with 21a);
the first terminals (Electrically connected with 13) of the first electrostatic discharge circuit (Comprising 17a) and the second electrostatic discharge circuit (Comprising 17b) are electrically connected to different first signal lines respectively (Comprising 14a, 14b); and
the second terminals (Electrically connected with 19a, 21a) of the first electrostatic discharge circuit (Comprising 17a) and the second electrostatic discharge circuit (Comprising 17b) are electrically connected to different power signal lines respectively (Comprising 19, 21), wherein
the plurality of electrostatic discharge circuits (Comprising 17a, 17b) is arranged along a first direction (Comprising +X, –X), and
the plurality of power signal lines (Comprising 19, 21, 23, 24) extend along the first direction (Comprising +X, –X) and
power signal lines (Comprising 19, 21, 23, 24) connected to the plurality of electrostatic discharge circuits (Comprising 17a, 17b) are disposed on sides of the plurality of electrostatic discharge circuits (Comprising 17a, 17b) along a second direction (Comprising +Y, –Y), and
the first direction (Comprising +X, –X) is perpendicular to the second direction (Comprising +Y, –Y).
Fujikawa does not explicitly disclose the apparatus wherein power signal lines are disposed on a same side of the plurality of electrostatic discharge circuits.
In the same field of endeavor, Liu teaches a display [0002] wherein power signal lines (Figure 6: Comprising VGL, VGH) are disposed on a same side of the plurality of electrostatic discharge circuits (Comprising ESDi2), an alternative to the configuration of power signal lines being formed on both sides of the electrostatic discharge circuits (Figure 10) each accommodating a respective one of device wiring schemes [0079]. The teaching by Liu of both power signal line configurations establishes that an Artisan would have been motivated to reconfigure the power signal lines positioning of Fujikawa in view of the teaching of Liu, with a reasonable expectation of success.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Fujikawa to be modified wherein power signal lines are disposed on a same side of the plurality of electrostatic discharge circuits, in view of the teaching of Liu, in view of the reasoning above.
Fujikawa does not explicitly disclose the panel wherein power signal lines are disposed on a same side of the plurality of electrostatic discharge circuits.
In the same field of endeavor, Liu teaches a display [0002] wherein power signal lines (Figure 6: Comprising VGL, VGH) are disposed on a same side of the plurality of electrostatic discharge circuits (Comprising ESDi3), an alternative to the configuration of power signal lines being formed on both sides of the electrostatic discharge circuits (Figure 10) each accommodating a respective one of device wiring schemes [0079]. The teaching by Liu of both power signal line configurations establishes that an Artisan would have been motivated to reconfigure the power signal lines positioning of Fujikawa in view of the teaching of Liu, with a reasonable expectation of success.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified wherein power signal lines are disposed on a same side of the plurality of electrostatic discharge circuits, in view of the teaching of Liu, in view of the reasoning above.
Fujikawa in view of Liu does not explicitly disclose the apparatus wherein a first power signal line connected to the first electrostatic discharge circuit has a voltage domain that matches a voltage domain of a first signal line connected to the first electrostatic discharge circuit, and a second power signal line connected to the second electrostatic discharge circuit has a voltage domain that matches a voltage domain of a second signal line connected to the second electrostatic discharge circuit.
In the same field of endeavor, Cho discloses a semiconductor device [0002] with electrostatic discharge protection included among interface cells [0042] disposed in the same power domain of a logic cell [0110]. The driver circuit (Figure 9: Comprising 530) is one the same voltage rails (Comprising VDD, VSS) as the ESD diode (Comprising 520). Driving circuitry may be powered with the same domain of voltage values applied to its corresponding electrostatic discharge protection circuitry. This is among measures implemented to reduce a routing path [0147] and preserve a uniform device thickness [0133].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified wherein a first power signal line connected to the first electrostatic discharge circuit has a voltage domain that matches a voltage domain of a first signal line connected to the first electrostatic discharge circuit, and a second power signal line connected to the second electrostatic discharge circuit has a voltage domain that matches a voltage domain of a second signal line connected to the second electrostatic discharge circuit, in view of the teaching of Cho, to preserve uniform device thickness.
ii. Claims 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over FLC, as applied to claim 1 above, and further in view of Park et al. (2022/0270544; hereinafter Park; this combination of references hereinafter referred to as FLCP).
Regarding claim 13, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel (Figure 1) further including: a plurality of pixel circuits (Comprising 7).
FLC does not explicitly disclose the panel further comprising a plurality of light-emitting elements, wherein: the plurality of pixel circuit include a pulse width modulation circuit and a pulse amplitude modulation circuit; the plurality of first signal lines include a first sub-signal line and a second sub-signal line; and the first sub-signal line is electrically connected to the first electrostatic discharge circuit and the pulse width modulation circuit; and the second sub-signal line is electrically connected to the second electrostatic discharge circuit and the pulse amplitude modulation circuit.
In the same field of endeavor, Park discloses a display [0002] comprising a plurality of light-emitting elements [0050], wherein: the plurality of pixel circuit include a pulse width modulation circuit and a pulse amplitude modulation circuit (Among external devices [0121] transmitting PWM and PAM voltages to respective input pads [0012]); the plurality of first signal lines include a first sub-signal line (Figure 10: Comprising L.sub.5) and a second sub-signal line (Comprising L.sub.6); and the first sub-signal line (Comprising L.sub.5) is electrically connected to the first electrostatic discharge circuit (Comprising 132) and the pulse width modulation circuit (External device [0121] transmitting PWM voltage [0012]); and the second sub-signal line (Comprising L.sub.6) is electrically connected to the second electrostatic discharge circuit (Comprising 132) and the pulse amplitude modulation circuit (External device [0121] transmitting PAM voltage [0012]). Fujikawa’s implementation extending beyond the disclosed display technology [0162] stands to benefit from Park’s efficient controller space allocation [0135].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified as further comprising a plurality of light-emitting elements, wherein: the plurality of pixel circuit include a pulse width modulation circuit and a pulse amplitude modulation circuit; the plurality of first signal lines include a first sub-signal line and a second sub-signal line; and the first sub-signal line is electrically connected to the first electrostatic discharge circuit and the pulse width modulation circuit; and the second sub-signal line is electrically connected to the second electrostatic discharge circuit and the pulse amplitude modulation circuit, in view of the teaching of Park, to more effectively allocate controller space.
Regarding claim 14, FLCP discloses the display panel according to claim 13.
Fujikawa does not explicitly disclose the panel wherein: the first sub-signal line is electrically connected to a signal line in the pulse width modulation circuit that needs electrostatic discharge; and the second sub-signal line is electrically connected to a signal line in the pulse amplitude modulation circuit that needs electrostatic discharge.
In the same field of endeavor, Park discloses a display [0002] wherein the first sub-signal line (Figure 10: Comprising L.sub.6) is electrically connected to a signal line in the pulse width modulation circuit that needs electrostatic discharge (External device [0121] transmitting PWM voltage [0012]); and the second sub-signal line is electrically connected to a signal line (Comprising L.sub.5) in the pulse amplitude modulation circuit that needs electrostatic discharge (External device [0121] transmitting PAM voltage [0012]). Fujikawa’s implementation extending beyond the disclosed display technology [0162] stands to benefit from Park’s efficient controller space allocation [0135].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified wherein the first sub-signal line is electrically connected to a signal line in the pulse width modulation circuit that needs electrostatic discharge; and the second sub-signal line is electrically connected to a signal line in the pulse amplitude modulation circuit that needs electrostatic discharge, in view of the teaching of Park, to more effectively allocate controller space.
iii. Claims 16 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over FLC, as applied to claim 3 above, and further in view of Kim et al. (2023/0107775; hereinafter Jeong; this combination of references hereinafter referred to as FLCJ).
Regarding claim 16, FLC discloses the display panel according to claim 3. Fujikawa discloses the panel (Figure 1) wherein, in the scan line driving circuit (Comprising 5), the first power terminal (Comprising one of 18, 22; [0040]) and the second power terminal (Comprising other one of 18, 22) are electrically connected to the first power signal line (At one end of current path formed across 31, 32) and the second power signal line (At other end of current path formed across 31, 32) in the first group of power signal lines respectively.
FLC does not explicitly disclose the panel further including: a plurality of cascaded first shift register circuits and a plurality of cascaded second shift register circuits, wherein a first shift register circuit includes a first power terminal and a second power terminal; a second shift register circuit includes a first power terminal and a second power terminal.
In the same field of endeavor, Jeong discloses a display [0002] comprising a plurality of cascaded first shift register circuits (Comprising a first one of 110 {Figure 21} comprising 113 {Figure 1} and its respective stages {Figure 13}) and a plurality of cascaded second shift register circuits (Comprising a second differing one of 110 {Figure 21} comprising 113 {Figure 1} and its respective stages {Figure 13}), wherein a first shift register circuit includes a first power terminal and a second power terminal (Aforementioned first one, whose respective stage {Figure 14} comprises VGHT, VGLT); a second shift register circuit includes a first power terminal and a second power terminal (Aforementioned second differing one, whose respective stage {Figure 14} comprises VGHT, VGLT). This is among measures preventing quality degradation resulting from improper driving [0004].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified as further comprising a plurality of cascaded first shift register circuits and a plurality of cascaded second shift register circuits, wherein a first shift register circuit includes a first power terminal and a second power terminal; a second shift register circuit includes a first power terminal and a second power terminal, in view of the teaching of Jeong, to prevent degrading image quality.
Regarding claim 17, FLCJ discloses the display panel according to claim 16. Fujikawa discloses the panel (Figure 1) further including: a plurality of pixel circuits (Comprising 7).
Fujikawa does not explicitly disclose the panel further including a plurality of light emitting elements, wherein: the plurality of pixel circuits includes a pulse width modulation circuit and a pulse amplitude modulation circuit; and an output terminal of the first shift register circuit is electrically connected to the pulse width modulation circuit, and an output terminal of the second shift register circuit is electrically connected to the pulse amplitude modulation circuit.
In the same field of endeavor, Jeong discloses a display [0002] comprising a plurality of light emitting elements (Figure 1: Comprising RP, GP, BP; [0028]), wherein: the plurality of pixel circuits (Figure 2) includes a pulse width modulation circuit (Comprising at least one of PDU1, PDU2) and a pulse amplitude modulation circuit (Comprising PDU3); and an output terminal of the first shift register circuit (Figure 13: Comprising SWPLx4, PWELx) is electrically connected to the pulse width modulation circuit (Comprising at least one of PDU1, PDU2), and an output terminal of the second shift register circuit is electrically connected to the pulse amplitude modulation circuit. This is among measures preventing quality degradation resulting from improper driving [0004].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified as further comprising a plurality of light emitting elements, wherein: the plurality of pixel circuits includes a pulse width modulation circuit and a pulse amplitude modulation circuit; and an output terminal of the first shift register circuit is electrically connected to the pulse width modulation circuit, and an output terminal of the second shift register circuit is electrically connected to the pulse amplitude modulation circuit, to prevent degrading image quality.
FLCJ does not expressly state providing the panel wherein an output terminal of the second shift register circuit is electrically connected to the pulse amplitude modulation circuit. However, please consider the following.
This omission within Jeong appears to be in favor of brevity. The invention of Jeong is drawn toward the sweep signal driver ([0002]; Comprising 113 of Figure 1), the only among scan driver (Comprising 110) sub-circuits (Comprising 111 – 114) for which substantial detail, including shift register (Figures 13, 14) connectivity, is furnished.
However, in light of Jeong’s admission that the emission signal driver (Comprising 114 of Figure 1) outputs PAM emission signals to PAM emission lines (PAEL; [0075]) connected to pixels’ third driving unit (Comprising PDU3 of Figure 2) and the known5 use of shift registers to output multiple gate line signals, it would not exceed the skill of an Artisan to modify Jeong’s aforementioned emission signal driver, as comprising shift register circuits (outputting PAM emission signals) to arrive at the claimed invention.
It would be obvious to one having ordinary skill in the art before the filling date of the claimed invention to modify the panel disclosed by (Fujikawa in view of) Jeong, to arrive at the claimed invention, in view of the reasoning above.
Regarding claim 18, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel (Figure 1) further including: a plurality of pixel circuits (Comprising 7), wherein the plurality of electrostatic discharge circuits (Comprising 17a, 17b) is between the plurality of pixel circuits (Comprising 7) and a first edge of the display panel (Comprising 2).
FLC does not explicitly disclose the panel comprising a plurality of light-emitting elements.
In the same field of endeavor, Jeong discloses a display [0002] comprising a plurality of light emitting elements (Figure 1: Comprising RP, GP, BP; [0028]). This is among measures preventing quality degradation resulting from improper driving [0004].
It would obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified as comprising a plurality of light-emitting elements, in view of the teaching of Jeong, to prevent image quality degradation.
Regarding claim 19, FLCJ discloses the display panel according to claim 18. Fujikawa discloses the panel (Figure 9) wherein: the first edge (Comprising 52a) is disposed with side wires (Of which lines {e.g. 16} and respective terminals {e.g. 16a} are comprised).
iv. Claims 21, 22 are rejected under 35 U.S.C. 103 as being unpatentable over FLC, as applied to claim 1 above, and further in view of Kim et al. (2021/0142748; hereinafter Kim).
Regarding claim 21, FLC discloses the display panel according to claim 1. Fujikawa discloses the panel (Figure 1) further including: a plurality of pixel circuits (Comprising 7).
FLC does not explicitly disclose the panel comprising a plurality of light-emitting elements, wherein: a same pixel circuit includes a first module and a second module; and the plurality of first signal lines include a first sub-signal line and a second sub-signal line; the first sub-signal line is electrically connected to the first electrostatic discharge circuit and the first module respectively; and the second sub-signal line is electrically connected to the second electrostatic discharge circuit and the second module respectively.
In the same field of endeavor, Kim discloses a display [0002] whose pixel circuits [0065] comprising light emitting elements [0100] under PWM and PAM driving [0096] voltages [0077] furnished among signals carried on wiring lines (Comprising 52 of Figure 2I; [0133]) furnishing electrostatic protection [0134]. The disclosed circuitry is among measures by which a display panel without a bezel may be protected from electrostatic discharge [0007].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified as comprising a plurality of light-emitting elements, wherein: a same pixel circuit includes a first module and a second module; and the plurality of first signal lines include a first sub-signal line and a second sub-signal line; the first sub-signal line is electrically connected to the first electrostatic discharge circuit and the first module respectively; and the second sub-signal line is electrically connected to the second electrostatic discharge circuit and the second module respectively, in view of the teaching of Kim, to implement ESD protection in a display without a bezel.
Regarding claim 22, FLC discloses the display panel according to claim 1.
FLC does not explicitly disclose the panel further including: a plurality of light-emitting elements, wherein the plurality of light-emitting elements is micro-light-emitting diodes.
In the same field of endeavor, Kim discloses a display [0002] a plurality of light-emitting elements [0100], wherein the plurality of light-emitting elements is micro-light-emitting diodes [0094]. The disclosed circuitry is among measures by which a display panel without a bezel may be protected from electrostatic discharge [0007].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified as comprising a plurality of light-emitting elements, wherein the plurality of light-emitting elements is micro-light-emitting diodes, in view of the teaching of Kim, to implement ESD protection in a display without a bezel.
v. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over FLCP, as applied to claim 14 above, and further in view of Kim.
Regarding claim 15, FLCP discloses the display panel according to claim 14.
Fujikawa does not explicitly disclose the panel wherein: a same second sub-signal line is electrically connected to one of a first scanning signal line, a second scanning signal line, a light-emitting control signal line and a data signal line of the pulse amplitude modulation circuit.
In the same field of endeavor, Park discloses a display [0002] wherein a same second sub-signal line (Figure 10: Comprising L.sub.5) is electrically connected to one of a first scanning signal line, a second scanning signal line, a light-emitting control signal line and a data signal line ([0156]: Transmitting data voltage) of the pulse amplitude modulation circuit (External device [0121] transmitting PAM voltage [0012]). Fujikawa’s implementation extending beyond the disclosed display technology [0162] stands to benefit from Park’s efficient controller space allocation [0135].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified wherein a same second sub-signal line is electrically connected to one of a first scanning signal line, a second scanning signal line, a light-emitting control signal line and a data signal line of the pulse amplitude modulation circuit, in view of the teaching of Park, to more effectively allocate controller space.
FLCP does not explicitly disclose the panel wherein: a same first sub-signal line is electrically connected to one of a first scanning signal line, a second scanning signal line, a light-emitting control signal line and a frequency-sweeping signal line of the pulse width modulation circuit.
In the same field of endeavor, Kim discloses a display [0002] wherein a same first sub-signal line (Figure 2I: Comprising 52) is electrically connected to one of a first scanning signal line, a second scanning signal line, a light-emitting control signal line and a frequency-sweeping signal line of the pulse width modulation circuit ([0162]: Transmitting dimming signal). The disclosed circuitry is among measures by which a display panel without a bezel may be furnished ESD protection [0007].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Fujikawa to be modified wherein a same first sub-signal line is electrically connected to one of a first scanning signal line, a second scanning signal line, a light-emitting control signal line and a frequency-sweeping signal line of the pulse width modulation circuit, in view of the teaching of Kim, to implement ESD protection in a display panel without a bezel.
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/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 Shown in plurality in e.g. Figure 3.
2 Shown in plurality in e.g. Figure 3.
3 Shown in plurality in e.g. Figure 3.
4 “…x…” is Examiner defined placeholder for the shown range of k…k+6.
5 See Choi et al. (2025/0166576) | Figure 24: Each among GPC outputting SC, SE signals.
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