The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 21-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11271870 (hereinafter P11271870). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following.
For claim 1, P11271870 discloses a system for supporting a bitmap based P_Key table in a high performance computing environment (claim 1 “A system for supporting a bitmap based P_Key table in a high performance computing environment”), comprising:
one or more microprocessors (claim 1 “one or more microprocessors”);
a subnet, the subnet comprising (claim 1 “at least one subnet, the at least one subnet comprising”):
a plurality of switches (claim 1, “a plurality of switches, …”),
a plurality of end nodes, the plurality of end nodes being interconnected via the plurality of switches (claim 1 “a plurality of end nodes, wherein each of the plurality of end nodes is associated with at least one host channel adapter of the plurality of host channel adapters; wherein each of the plurality of end nodes is associated with at least one of a plurality of partitions;”; note for end nodes must interconnected via switches in order to be associated with partitions);
a subnet manager (claim 2 “The system of claim 1, further comprising: a subnet manager”);
wherein a switch of the plurality of switches receives, at a switch port of a plurality of switch ports of the switch, a packet comprising a header, the header comprising a partition key (P Key) associated with a partition of a plurality of partitions defined within the subnet (claim 1 “… wherein upon a switch port of a switch at non-leaf level receiving a packet from a sending end node, the packet comprising a header comprising a destination local identifier (DLID) of a receiving end node and a P_Key value indicating the sending end node belongs to a partition being associated with the P_Key, …” );
wherein the switch of the plurality of switches performs, at the switch port, a partition enforcement action (claim 1 “wherein upon a switch port of a switch at non-leaf level receiving a packet from a sending end node, the packet comprising a header comprising a destination local identifier (DLID) of a receiving end node and a P_Key value indicating the sending end node belongs to a partition being associated with the P_Key, …”); and
wherein the partition enforcement action comprises indexing the P Key of the receiving packet into a bitmap stored at a memory of the switch to determine a value of allowed or disallowed (claim 1, “… the another sending end node being a limited member of the partition, the at least one bitmap is indexed by the P_Key value of the header of the received another packet to determine a disallowed value for the another received packet”).
Claim 27 is rejected because it is a claim of a method performed by the system of claim 1 and has the same subject matter.
Claim 34 is rejected because it is a claim of a non-transitory computer readable storage medium having instructions for performing the method of claim 27 and has the same subject matter.
Each of dependent claims is rejected in a similar fashion to the corresponding independent claim.
Claims 1 and 21-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12120043 (hereinafter P12120043). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following.
For claim 1, P12120043 discloses a system for supporting a bitmap based P_Key table in a high performance computing environment (claim 1 “A system for supporting a bitmap based P_Key table in a high performance computing environment”), comprising:
one or more microprocessors (claim 1 “one or more microprocessors”);
a subnet, the subnet comprising (claim 1 “at least one subnet, the at least one subnet comprising”):
a plurality of switches (claim 1, “a plurality of switches, each of the plurality of switches comprising a plurality of switch ports …”),
a plurality of end nodes, the plurality of end nodes being interconnected via the plurality of switches (claim 1 “a plurality of end nodes, the plurality of end nodes being interconnected via the plurality of switches;”);
a subnet manager (claim 1 “a subnet manager;”);
wherein a switch of the plurality of switches receives, at a switch port of a plurality of switch ports of the switch, a packet comprising a header, the header comprising a partition key (P Key) associated with a partition of a plurality of partitions defined within the subnet (claim 1 “… wherein a first end node of the plurality of end nodes sends a packet, the packet comprising a header comprising a partition key (P_Key), … through a plurality of switch ports of two or more switches of the plurality of switches, …” );
wherein the switch of the plurality of switches performs, at the switch port, a partition enforcement action (claim 1 “… through a plurality of switch ports of two or more switches of the plurality of switches, … wherein the P_Key of the packet header is indexed into a bitmap at each of the plurality of switch ports”); and
wherein the partition enforcement action comprises indexing the P Key of the receiving packet into a bitmap stored at a memory of the switch to determine a value of allowed or disallowed (claim 1, “… wherein the P_Key of the packet header is indexed into a bitmap at each of the plurality of switch ports to determine whether to allow or disallow the packet to traverse through each of the plurality of switch ports.”).
Claim 27 is rejected because it is a claim of a method performed by the system of claim 1 and has the same subject matter.
Claim 34 is rejected because it is a claim of a non-transitory computer readable storage medium having instructions for performing the method of claim 27 and has the same subject matter.
Each of dependent claims is rejected in a similar fashion to the corresponding independent claim.
Claims 1 and 21-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11770349 (hereinafter P11770349 ). Although the claims at issue are not identical, they are not patentably distinct from each other because of the following.
For claim 1, P 11770349 discloses a system for supporting a bitmap based P_Key table in a high performance computing environment (claim 1 “A system for supporting legacy P_Key table abstraction using a bitmap based hardware implementation in a high performance computing environment”), comprising:
one or more microprocessors (claim 1 “one or more microprocessors”);
a subnet, the subnet comprising (claim 1 “at least one subnet, the at least one subnet comprising”):
a plurality of switches (claim 1, “a plurality of switches …”),
a plurality of end nodes, the plurality of end nodes being interconnected via the plurality of switches (claim 1 “… each of the end nodes access the at least one subnet via at least one host channel adapter of the plurality of host channel adapters, and a plurality of hardware-based P_Key tables, each of the plurality of hardware-based P_Key tables being provided at a respective switch of the plurality of switches; …”);
a subnet manager (claim 1 “… a subnet manager; …”);
wherein a switch of the plurality of switches receives, at a switch port of a plurality of switch ports of the switch, a packet comprising a header, the header comprising a partition key (P Key) associated with a partition of a plurality of partitions defined within the subnet (claim 1 “… each of the one or more switches comprise a plurality of switch ports, a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port, a plurality of end nodes, wherein each of the plurality of end nodes access the at least one subnet via at least one host channel adapter of the plurality of host channel adapters, and a plurality of hardware-based P_Key tables, each of the plurality of hardware-based P_Key tables being provided at a respective switch of the plurality of switches, …” and claim 3 “The system of claim 2, wherein the subnet manager configures, via the associated virtual P_Key table, the hardware-based P_Key bitmap based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the plurality of switches.”; note that traffic suggests packets and each packet has a header which must include a P_Key for switching);
wherein the switch of the plurality of switches performs, at the switch port, a partition enforcement action (claim 1 “…each of the one or more switches comprise a plurality of switch ports, a plurality of host channel adapters, each host channel adapter comprising at least one host channel adapter port, a plurality of end nodes, wherein each of the plurality of end nodes access the at least one subnet via at least one host channel adapter of the plurality of host channel adapters, and a plurality of hardware-based P_Key tables, each of the plurality of hardware-based P_Key tables being provided at a respective switch of the plurality of switches, …”; note that a P_Key suggests a partition enforcement action by definition); and
wherein the partition enforcement action comprises indexing the P Key of the receiving packet into a bitmap stored at a memory of the switch to determine a value of allowed or disallowed (claim 3, “The system of claim 2, wherein the subnet manager configures, via the associated virtual P_Key table, the hardware-based P_Key bitmap based upon the determination of allowed and disallowed traffic through each of the plurality of ports on each of the plurality of switches.”).
Claim 27 is rejected because it is a claim of a method performed by the system of claim 1 and has the same subject matter.
Claim 34 is rejected because it is a claim of a non-transitory computer readable storage medium having instructions for performing the method of claim 27 and has the same subject matter.
Each of dependent claims is rejected in a similar fashion to the corresponding independent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jianye Wu whose telephone number is (571)270-1665. The examiner can normally be reached on Monday to Thursday, 8am to 7pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yemane Mesfin can be reached on (571) 272-3927. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JIANYE WU/Primary Examiner, Art Unit 2462
Prosecution Insights