Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 22nd, 2026 has been entered.
Response to Arguments
2. Applicant’s arguments, filed June 22nd, 2026, with respect to the rejections of the independent claims under 35 U.S.C. 103 have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Sazegari et al (US 2005/0289519).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 21-22 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Alsup (US 2018/0357043) in view of Sharma et al (US 2020/0226473, herein Sharma), Ahmed et al (US 2008/0209184, herein Ahmed), and Sazegari et al (US 2005/0289519, cited in previous Office Action, herein Sazegari).
Regarding claim 21, Alsup teaches a compute unit comprising:
multiple hardware function units ([0375], transcendental units 800), each to implement one or more transcendental functions ([0214], [0375], [0428], [0458], identifying transcendental function operations and utilizing transcendental function unit); and
allocate transcendental function instructions to the multiple hardware function units for execution on an accelerated path ([0214], [0375], [0428], [0458], execution of transcendental functions on specialized transcendental function units).
Alsup fails to teach wherein the processor uses reconfigurable hardware function units, or uses a hardware-based scheduler to allocate the instructions.
Sharma discloses a system comprising a processor configured to use multiple reconfigurable hardware function units to execute transcendental functions on an accelerated path ([0069-0070], using specialized FPGAs for transcendental functions, [0073], [0137], accelerator for transcendental functions using reconfigurable architecture).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alsup and Sharma to utilize reconfigurable function units. While Alsup does not explicitly state that the transcendental function units are part of a group of reconfigurable units, Alsup does disclose some reconfigurability in the transcendental function units depending on their usage (Alsup [0384]). As both reconfigurable architecture and specialized accelerators are routine and conventional aspects of the microprocessor art, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Alsup and Sharma fail to disclose the compute unit using a hardware-based scheduler to allocate the instructions.
Ahmed discloses a system comprising a processor configured to use multiple reconfigurable hardware function units to execute transcendental functions on an accelerated path ([0021], reconfigurable floating point unit & [0004], using floating point unit for transcendental functions) using a hardware-based scheduler ([0016], scheduling unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alsup and Sharma with those of Ahmed to utilize a hardware scheduler. While neither Alsup nor Sharma explicitly state that the exemplary processors may include a hardware scheduler, one of ordinary skill in the art would understand that virtually all modern processors include some form of scheduling hardware to handle the issuing and management of instructions within a processor pipeline. As all three references disclose the use of specialized function units for performing transcendental functions, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Alsup, Sharma, and Ahmed fail to teach wherein the marked instructions comprise a marker inserted at compile time, and wherein the marked instructions are identified at runtime based on the marker and allocated to the multiple reconfigurable hardware function units responsive to identifying the marker.
Sazegari teaches a system comprising a processor wherein marked instructions comprise a marker inserted at compile time, and wherein the marked instructions are transcendental functions identified at runtime based on the marker and allocated to multiple hardware function units responsive to identifying the marker ([0012], [0018], claim 12, compiler-identified transcendental functions for execution on a GPU).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alsup, Sharma, and Ahmed with those of Sazegari to utilize compiler directed optimizations. While Alsup does disclose the use of a compiler for efficiently constructing coefficient tables for use in transcendental functions and Sharma teaches the exemplary FPGA utilizing compiler optimizations, neither explicitly states that these optimizations may include marking or annotating the source code. However, as compiler based annotation of source code is a routine and conventional aspect of the microprocessor art, and all three references disclose the use of compilation techniques for performing transcendental functions, the combination would merely entail a simple substitution of known prior art techniques to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 22, the combination of Alsup, Sharma, Ahmed and Sazegari teaches the compute unit of claim 21, wherein each reconfigurable hardware function unit is programmable at runtime to implement different transcendental functions selected from exponential, logarithmic, trigonometric, or hyperbolic functions (Ahmed [0004], exponential & trigonometric calculations by reconfigurable FPU, Alsup [0085], [0097], [0405], logarithmic, exponential, trigonometric functions).
Regarding claim 23, the combination of Alsup, Sharma and Ahmed teaches the compute unit of claim 21, wherein each reconfigurable hardware function unit is programmed using a table-and-addition-based accelerated function (Alsup [0029-0030], configuration tables, [0310], [0362], multiplication & addition operations).
Regarding claim 24, the combination of Alsup, Sharma, Ahmed and Sazegari teaches the compute unit of claim 21, wherein the hardware-based scheduler is configured to prioritize allocation of transcendental functions based on invocation frequency (Sharma [0069-0070], [0128-0130], [0137], FPGA use for transcendental functions & programming of FPGA by scheduler & Ahmed [0022], FPU scheduler).
Regarding claim 25, the combination of Alsup, Sharma, Ahmed and Sazegari teaches the compute unit of claim 21, wherein the hardware-based scheduler is configured to dynamically reconfigure the reconfigurable hardware function units for different transcendental functions between successive kernels (Alsup [0384] & Sharma [0063], [0067], computation kernels to control use of reconfigurable units).
Regarding claim 26, the combination of Alsup, Sharma, Ahmed and Sazegari teaches the compute unit of claim 21, wherein the multiple reconfigurable hardware function units are configured to reduce register pressure and floating-point unit utilization during execution of the transcendental function instructions (Alsup [0027-0028], [0048-0049], dedicated transcendental function unit to reduce impact on floating point unit).
3. Claims 1-4, 6-9, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Alsup (US 2018/0357043) in view of Sharma et al (US 2020/0226473, herein Sharma), and Sazegari et al (US 2005/0289519, cited in previous Office Action, herein Sazegari).
Regarding claim 1, Alsup teaches a system comprising:
at least one physical processor ([0029], [0458], claim 1, processor); and
physical memory comprising computer-executable instructions that, when executed by the physical processor, cause the physical processor (Figs 1-2, HDD, RAM, ROM, instruction & data memory, [0214], [0375], instructions) to:
identify one or more transcendental functions and instructions ([0214], [0375], [0428], [0458], identifying transcendental function operations and utilizing transcendental function unit); and
execute, at runtime, the identified transcendental functions on an accelerated path reserved for execution of transcendental functions by allocating the marked instructions to multiple hardware function units ([0214], [0375], [0428], [0458], execution of transcendental functions on specialized transcendental function units).
Alsup fails to teach wherein the processor executes the instructions reconfigurable hardware function units.
Sharma discloses a system comprising a processor configured to use multiple reconfigurable hardware function units to execute transcendental functions on an accelerated path ([0069-0070], using specialized FPGAs for transcendental functions, [0073], [0137], accelerator for transcendental functions using reconfigurable architecture).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alsup and Sharma to utilize reconfigurable function units. While Alsup does not explicitly state that the transcendental function units are part of a group of reconfigurable units, Alsup does disclose some reconfigurability in the transcendental function units depending on their usage (Alsup [0384]). As both reconfigurable architecture and specialized accelerators are routine and conventional aspects of the microprocessor art, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Alsup and Sharma fail to teach identifying the transcendental functions in source code at compile time and marking a block of instructions that contain the one or more transcendental functions as marked instructions, or wherein the marked instructions comprise a marker inserted at compile time, and wherein the marked instructions are identified at runtime based on the marker and allocated to the multiple reconfigurable hardware function units responsive to identifying the marker.
Sazegari teaches a system comprising a processor configured to identify the transcendental functions in source code at compile time and marking a block of instructions that contain the one or more transcendental functions as marked instructions wherein marked instructions comprise a marker inserted at compile time, and wherein the marked instructions are identified at runtime based on the marker and allocated to multiple hardware function units responsive to identifying the marker ([0012], [0018], claim 12, compiler-identified transcendental functions for execution on a GPU).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alsup, Sharma, and Ahmed with those of Sazegari to utilize compiler directed optimizations. While Alsup does disclose the use of a compiler for efficiently constructing coefficient tables for use in transcendental functions and Sharma teaches the exemplary FPGA utilizing compiler optimizations, neither explicitly states that these optimizations may include marking or annotating the source code. However, as compiler based annotation of source code is a routine and conventional aspect of the microprocessor art, and all three references disclose the use of compilation techniques for performing transcendental functions, the combination would merely entail a simple substitution of known prior art techniques to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 1, wherein the physical processor is a graphics processing unit (GPU) (Alsup [0359], Sharma [0077], GPU).
Regarding claim 3, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 2, wherein the accelerated path is different than paths used to processing existing GPU instructions (Sharma [0073], [0137], accelerator path using FPGA).
Regarding claim 4, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 1, wherein the multiple reconfigurable hardware function units are programmed with a table and addition based accelerated function (Alsup [0029-0030], configuration tables, [0310], [0362], multiplication & addition operations).
Regarding claim 6, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 1, wherein the marker comprises at least one of metadata or a specific opcode that indicates the marked instructions belong to a transcendental function block (Sazegari [0012], [0018], claim 12, compiler-identified transcendental functions for execution on a GPU).
Regarding claim 7, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 6, wherein the accelerated path performs processing related to the marked instruction only, and does not perform other GPU instructions including arithmetic instructions, logical instructions, memory instructions, control flow instructions, or synchronization instructions (Alsup [0048-0049], transcendental calculation unit exclusively for use with transcendental functions).
Regarding claim 8, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 1, wherein a hardware-based scheduler triggers programming of the multiple reconfigurable hardware function units (Sharma [0128-0130], [0137], programming FPGA using scheduler).
Regarding claim 9, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 8, wherein the programming of the multiple reconfigurable hardware function units occurs at a next invocation of a transcendental function from the one or more transcendental function (Sharma [0069-0070], [0128-0130], [0137], FPGA use for transcendental functions & programming of FPGA by scheduler).
Claims 17, 18, 19, and 20 refer to a method embodiment of the system embodiment of claims 1, 3, 4, and 8, respectively. Therefore, the above rejections for claims 1, 3, 4, and 8 are applicable to claims 17, 18, 19, and 20, respectively.
4. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Alsup, Sharma, and Sazegari as applied to claim 1 above, and further in view of Davis et al (US 2023/0305993, herein Davis).
Regarding claim 5, the combination of Alsup, Sharma, and Sazegari teaches the system of claim 1. Alsup, Sharma, and Sazegari fail to teach wherein a number of the multiple reconfigurable hardware function units is based on chip area and power budget.
Davis teaches a system configured to execute transcendental functions ([0129], transcendental math functions) wherein a number of multiple configurable hardware function units is based on chip area and power budget ([0191], [0225], [0248], [0251], [0258], configuring chip with a number of functional units according to available silicon area and power metric or consumption of chip).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alsup, Sharma, and Sazegari with those of Davis to configure the system according to size and power requirements. While Alsup and Sharma do not explicitly state that the reconfiguration of the hardware functional units may be based on metrics like size or power budget, Alsup does disclose accounting for configuring the chip in order to increase efficiency and reduce power cost. As one of ordinary skill in the art would understand, the relationship between a number of active hardware units and the corresponding need for more chip area and power consumption is a routine and conventional aspect of the microprocessor art. Therefore, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results and would have been obvious to one of ordinary skill in the art.
5. Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Alsup, Sharma, Ahmed and Sazegari as applied to claim 21 above, and further in view of Davis et al (US 2023/0305993, herein Davis).
Regarding claim 27, the combination of Alsup, Sharma, Ahmed and Sazegari teaches the compute unit of claim 21. Alsup, Sharma, Ahmed and Sazegari fail to teach wherein a number of the multiple reconfigurable hardware function units is based on chip area and power budget.
Davis teaches a system configured to execute transcendental functions ([0129], transcendental math functions) wherein a number of multiple configurable hardware function units is based on chip area and power budget ([0191], [0225], [0248], [0251], [0258], configuring chip with a number of functional units according to available silicon area and power metric or consumption of chip).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Alsup, Sharma, Ahmed and Sazegari with those of Davis to configure the system according to size and power requirements. While Alsup and Sharma do not explicitly state that the reconfiguration of the hardware functional units may be based on metrics like size or power budget, Alsup does disclose accounting for configuring the chip in order to increase efficiency and reduce power cost. As one of ordinary skill in the art would understand, the relationship between a number of active hardware units and the corresponding need for more chip area and power consumption is a routine and conventional aspect of the microprocessor art. Therefore, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results and would have been obvious to one of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tang (US 2004/0215676) discloses a processor for identifying transcendental functions at compile time.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
