DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khan et al. 20180089119 herein Khan.
Per claim 1, Khan discloses: A device virtualization method performed by a device end, wherein the device end (logic platform) is communicatively connected to a host end (server) of an accelerated computing system, and the method comprises: (fig. 1) receiving, by the device end, a management command from the host end, wherein the management command is used to virtualize a physical resource in the device end to provide a virtual function to the host end for use, and the physical resource is used to perform an accelerated computing task; (¶0023;The host logic can include the management function 114 that can be used for managing and configuring the configurable logic platform 110. Commands and data can be sent from the server computer 120 to the management function 114 using transactions that target the address range of the management function 114. For example, the server computer 120 can generate transactions to transfer data (e.g., configuration data) and/or write control registers of the configurable logic platform 110 that are mapped to one or more addresses within the address range of the management function 114. ¶0020; Each reconfigurable logic region 140A-B can include hardware that is configurable to implement a hardware accelerator or application logic. In other words, each reconfigurable logic region 140A-B can include logic that is programmable to perform a given function.) and configuring, by the device end, a register in the device end based on the management command, wherein the register is configured to virtualize the physical resource (¶0023; Writing the control registers can cause the configurable logic platform 110 to perform operations, such as configuring and managing the configurable logic platform 110. As a specific example, configuration data corresponding to application logic to be implemented in the reconfigurable logic region 140 can be transmitted from the server computer 120 to the configurable logic platform 110 in one or more transactions over the physical interconnect… the server computer 120 can generate transactions to transfer data (e.g., configuration data) and/or write control registers of the configurable logic platform 110 that are mapped to one or more addresses within the address range of the management function 114.).
Claim 6 is the device claim corresponding to the method claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-5, 7-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Kakaiya et al. 20180321985 herein Kakaiya.
Per claim 2, Khan discloses accelerated computing tasks but does not specifically disclose: the method further comprising: transmitting, by the device end, an accelerated computing task to the host end by using a queue, wherein the queue is virtually presented by the device end to the host end, and the accelerated computing task is stored in a memory in the device end.
However, Kakaiya discloses: the method further comprising: transmitting, by the device end, an accelerated computing task to the host end by using a queue, wherein the queue is virtually presented by the device end to the host end, and the accelerated computing task is stored in a memory in the device end (¶0053; the Scalable IOV architecture 150 can include an emulated configuration space for assignable entities, virtualized interrupt configuration for assignable entities, direct-mapped fast-path registers, virtualized slow-path operations, OS/VMM-agnostic software-based communication between guest and host drivers, virtualized functional level reset for assignable entities, software-defined device-specific front-end resource (e.g., MMIO, Interrupt) to back-end resource mapping (e.g., Network Interface Card (NIC) receive/transmit (Rx/Tx) queues, storage command queues, graphics processing unit (GPU) contexts, contexts for accelerators or Accelerator Function Units (AFUs)), dynamic and fine-grained resource sharing, etc).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Khan and Kakaiya’s scalable vitualizaion of I/O devices to enable finer grained and scalable virtualization. Kakaiya increases flexibility (¶0056).
Per claim 3, Kakaiya discloses: wherein the accelerated computing task comprises at least one of the following: a graphics accelerated computing task, a vector operation accelerated computing task, a matrix operation accelerated computing task, a data copy accelerated computing task, or a video encoding and decoding accelerated computing task (¶0053, ¶0179; In one embodiment, one or more additional processor(s) 1415, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus 1416.).
Per claim 4, Kakaiya discloses: wherein the register is configured with at least one of the following: a quantity of virtual functions; a mapping relationship between a virtual memory of the virtual function and a physical memory in the device end; a mapping relationship between a queue of the virtual function and a memory address in the device end, wherein the queue is virtually presented by the device end to the host end, the queue is used by the host end to transmit the accelerated computing task and indication information to the device end, and the indication information indicates whether the device end completes the accelerated computing task; or quantities of accelerators of different types in an accelerator group of the virtual function (fig. 3, ¶0096-97; for a network controller device, an AI (e.g., AI instance 310A) may be composed of a set of Tx/Rx queues associated with a Virtual Switch Interface (VSI). Additionally, an AI on a NVM Express (NVMe, or Non-Volatile Memory Host Controller Interface Specification (NVMHCI)) storage controller could be the bundle/set of command queues (and respective completion queues) associated with a common storage namespace. For a GPU, an AI could be the set of GPU contexts created through a Virtual Device (vGPU) instance. For an FPGA device, each AI could be an entire Accelerator Function Unit (AFU) or a context of a multi-context capable AFU).
Per claim 5, Kakaiya discloses: wherein there are a plurality of virtual functions, and different virtual functions correspond to different physical resources (fig. 3, ¶0096-97; for a network controller device, an AI (e.g., AI instance 310A) may be composed of a set of Tx/Rx queues associated with a Virtual Switch Interface (VSI). Additionally, an AI on a NVM Express (NVMe, or Non-Volatile Memory Host Controller Interface Specification (NVMHCI)) storage controller could be the bundle/set of command queues (and respective completion queues) associated with a common storage namespace. For a GPU, an AI could be the set of GPU contexts created through a Virtual Device (vGPU) instance. For an FPGA device, each AI could be an entire Accelerator Function Unit (AFU) or a context of a multi-context capable AFU).
Claim 7-10 are the device claims corresponding to the method claims 2-5 and are rejected under the same reasons set forth in connection with the rejection of claims 2-5.
Per claim 11, Khan discloses: A device virtualization method, wherein the method is applied to an accelerated computing system, the accelerated computing system comprises a host end and a device end communicatively connected to the host end, and the method comprises: (fig. 1) transmitting, by the device end, an accelerated computing task to the host end by using…. of a virtual function presented by the device end on the host end, wherein the accelerated computing task is performed by an accelerator that corresponds to the accelerated computing task and that is in the device end, (¶0023;The host logic can include the management function 114 that can be used for managing and configuring the configurable logic platform 110. Commands and data can be sent from the server computer 120 to the management function 114 using transactions that target the address range of the management function 114. For example, the server computer 120 can generate transactions to transfer data (e.g., configuration data) and/or write control registers of the configurable logic platform 110 that are mapped to one or more addresses within the address range of the management function 114. ¶0020; Each reconfigurable logic region 140A-B can include hardware that is configurable to implement a hardware accelerator or application logic. In other words, each reconfigurable logic region 140A-B can include logic that is programmable to perform a given function.) and configuring, by the device end, a register in the device end based on the management command, wherein the register is configured to virtualize the physical resource (¶0023; Writing the control registers can cause the configurable logic platform 110 to perform operations, such as configuring and managing the configurable logic platform 110. As a specific example, configuration data corresponding to application logic to be implemented in the reconfigurable logic region 140 can be transmitted from the server computer 120 to the configurable logic platform 110 in one or more transactions over the physical interconnect… the server computer 120 can generate transactions to transfer data (e.g., configuration data) and/or write control registers of the configurable logic platform 110 that are mapped to one or more addresses within the address range of the management function 114.).
Khan discloses accelerated computing tasks but does not specifically disclose: a queue of a virtual function presented by the device end on the host end ; the queue is virtually presented by the device end to the host end, and the accelerated computing task is stored in a memory in the device end.
However, Kakaiya discloses: a queue of a virtual function presented by the device end on the host end ; the queue is virtually presented by the device end to the host end, and the accelerated computing task is stored in a memory in the device (¶0053; the Scalable IOV architecture 150 can include an emulated configuration space for assignable entities, virtualized interrupt configuration for assignable entities, direct-mapped fast-path registers, virtualized slow-path operations, OS/VMM-agnostic software-based communication between guest and host drivers, virtualized functional level reset for assignable entities, software-defined device-specific front-end resource (e.g., MMIO, Interrupt) to back-end resource mapping (e.g., Network Interface Card (NIC) receive/transmit (Rx/Tx) queues, storage command queues, graphics processing unit (GPU) contexts, contexts for accelerators or Accelerator Function Units (AFUs)), dynamic and fine-grained resource sharing, etc).
Claim 12-14 are the method claims corresponding to the method claims 2-5 and are rejected under the same reasons set forth in connection with the rejection of claims 2-5.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights