DETAILED ACTION
This office action is responsive to application 18/915,529 filed on October 15, 2024. Claims 1-15 are pending in the application and have been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed on November 13, 2024 was received and has been considered by the Examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 15/733,126, filed on May 21, 2020.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, 12 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoshida et al. (US 2018/0288346).
Consider claim 1, Yoshida et al. teaches:
A light detecting device (see figures 1 and 2), comprising:
a first pixel unit (For instance, a pixel (100) from the left column of pixels (100) in figure 1, paragraph 0021.) that includes (see figure 2):
a first photodiode (PD, paragraph 0024);
a first transfer transistor (transfer transistor, Mtx) coupled to the first photodiode (PD, see figure 2, paragraph 0043);
a first amplification transistor (pixel transistor Mpx, paragraph 0042) having a gate terminal coupled to the first transfer transistor (Mtx, see figure 2); and
a first selection transistor (selection transistor, Msx, paragraph 0042) coupled to the first amplification transistor (Mpx, see figure 2);
a second pixel unit (For instance, another pixel (100) from the left column of pixels (100) in figure 1, paragraph 0021.) that includes (see figure 2):
a second photodiode (PD, paragraph 0024);
a second transfer transistor (transfer transistor, Mtx) coupled to the second photodiode (PD, see figure 2, paragraph 0043);
a second amplification transistor (pixel transistor Mpx, paragraph 0042) having a gate terminal coupled to the second transfer transistor (Mtx, see figure 2); and
a second selection transistor (selection transistor, Msx, paragraph 0042) coupled to the second amplification transistor (Mpx, see figure 2); and
an analog to digital (AD) converter (see figures 1 and 2) that includes a first metal oxide semiconductor (MOS) transistor (differential transistor, M3, figure 2) to which a reference signal (VRMP) is input (see figure 2, paragraph 0025), wherein
the first pixel unit (100) and the second pixel unit (100) share the AD converter (i.e. due to one AD converter being provided per pixel column, see figure 1),
each of the first transfer transistor (Mtx) and the second transfer transistor (Mtx) is configured to enter into an ON state at a first timing (Each transfer transistor (Mtx) is configured to enter an ON state at a first timing as each transfer transistor (Mtx) includes a gate terminal to which at which a control signal (ΦT) is input, see figure 2, paragraph 0042. For instance, each transfer transistor (Mtx) enters an ON state at timing t2 of figure 3.),
the first selection transistor (Msx) is configured to enter into an ON state at a second timing (Each selection transistor (Msx) is configured to enter an ON state at a second timing as each selection transistor (Msx) includes a gate terminal to which a control signal (ΦSEL) is input, see figure 2, paragraph 0042. For instance, each selection transistor (Msx) is configured to enter an ON state at timing t0 of figure 3.), and
the second selection transistor (Msx) is configured to enter into an ON state at a third timing (Each selection transistor (Msx) is configured to enter an ON state at a third timing as each selection transistor (Msx) includes a gate terminal to which a control signal (ΦSEL) is input, see figure 2, paragraph 0042. For instance, each selection transistor (Msx) is configured to enter an ON state at timing t4 of figure 3.).
The Examiner notes that the first transfer transistor, second transfer transistor, first selection transistor and second selection transistor are each recited as being “configured to enter an ON state”. Because each of these transistors includes a gate terminal, each transistor is configured to enter an ON state. Claim 1 is directed toward an apparatus (“A light detecting device”). As detailed in MPEP 2114(II), a method of operating a device does not differentiate an apparatus claim from the prior art. MPEP 2114(II) states, “A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)”. Yoshida et al. teaches all of the structural limitations of claim 1, as discussed above. Claim 1, as currently written, does not require that the first transfer transistor, second transfer transistor, first selection transistor and second selection transistor are operated at specific timings, as these recitations are not directed toward the structure of the apparatus, but rather are directed toward the manner in which the claimed apparatus is operated.
Consider claim 12, Yoshida et al. teaches:
An electronic device (photoelectric conversion apparatus, figure 1) comprising:
a light detecting device (see figures 1 and 2), comprising:
a first pixel unit (For instance, a pixel (100) from the left column of pixels (100) in figure 1, paragraph 0021.) that includes (see figure 2):
a first photodiode (PD, paragraph 0024);
a first transfer transistor (transfer transistor, Mtx) coupled to the first photodiode (PD, see figure 2, paragraph 0043);
a first amplification transistor (pixel transistor Mpx, paragraph 0042) having a gate terminal coupled to the first transfer transistor (Mtx, see figure 2); and
a first selection transistor (selection transistor, Msx, paragraph 0042) coupled to the first amplification transistor (Mpx, see figure 2);
a second pixel unit (For instance, another pixel (100) from the left column of pixels (100) in figure 1, paragraph 0021.) that includes (see figure 2):
a second photodiode (PD, paragraph 0024);
a second transfer transistor (transfer transistor, Mtx) coupled to the second photodiode (PD, see figure 2, paragraph 0043);
a second amplification transistor (pixel transistor Mpx, paragraph 0042) having a gate terminal coupled to the second transfer transistor (Mtx, see figure 2); and
a second selection transistor (selection transistor, Msx, paragraph 0042) coupled to the second amplification transistor (Mpx, see figure 2); and
an analog to digital (AD) converter (see figures 1 and 2) that includes a first metal oxide semiconductor (MOS) transistor (differential transistor, M3, figure 2) to which a reference signal (VRMP) is input (see figure 2, paragraph 0025), wherein
the first pixel unit (100) and the second pixel unit (100) share the AD converter (i.e. due to one AD converter being provided per pixel column, see figure 1),
each of the first transfer transistor (Mtx) and the second transfer transistor (Mtx) is configured to enter into an ON state at a first timing (Each transfer transistor (Mtx) is configured to enter an ON state at a first timing as each transfer transistor (Mtx) includes a gate terminal to which at which a control signal (ΦT) is input, see figure 2, paragraph 0042. For instance, each transfer transistor (Mtx) enters an ON state at timing t2 of figure 3.),
the first selection transistor (Msx) is configured to enter into an ON state at a second timing (Each selection transistor (Msx) is configured to enter an ON state at a second timing as each selection transistor (Msx) includes a gate terminal to which a control signal (ΦSEL) is input, see figure 2, paragraph 0042. For instance, each selection transistor (Msx) is configured to enter an ON state at timing t0 of figure 3.), and
the second selection transistor (Msx) is configured to enter into an ON state at a third timing (Each selection transistor (Msx) is configured to enter an ON state at a third timing as each selection transistor (Msx) includes a gate terminal to which a control signal (ΦSEL) is input, see figure 2, paragraph 0042. For instance, each selection transistor (Msx) is configured to enter an ON state at timing t4 of figure 3.).
The Examiner notes that the first transfer transistor, second transfer transistor, first selection transistor and second selection transistor are each recited as being “configured to enter an ON state”. Because each of these transistors includes a gate terminal, each transistor is configured to enter an ON state. Claim 12 is directed toward an apparatus (“An electronic device”). As detailed in MPEP 2114(II), a method of operating a device does not differentiate an apparatus claim from the prior art. MPEP 2114(II) states, “A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)”. Yoshida et al. teaches all of the structural limitations of claim 12, as discussed above. Claim 12, as currently written, does not require that the first transfer transistor, second transfer transistor, first selection transistor and second selection transistor are operated at specific timings, as these recitations are not directed toward the structure of the apparatus, but rather are directed toward the manner in which the claimed apparatus is operated.
Consider claims 11 and 14, and as applied to claims 1 and 12 above, Yoshida et al. further teaches that the second timing is subsequent to the first timing (For instance, each selection transistor (Msx) is configured to enter an ON state at timing t0 of figure 3. A timing t0 of a second frame is subsequent to the first timing t2 of a first frame.), and the third timing is subsequent to the second timing (A third timing (t4) of a second frame is subsequent to the second timing (t0) of the second frame, see figure 3.).
Claims 11 and 14 are directed toward an apparatus (“A light detecting device”). As detailed in MPEP 2114(II), a method of operating a device does not differentiate an apparatus claim from the prior art. MPEP 2114(II) states, “A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)”. Yoshida et al. teaches all of the structural limitations of claims 11 and 14, respectively, as discussed above. Claims 11 and 14, as currently written, do not require that the first transfer transistor, second transfer transistor, first selection transistor and second selection transistor are operated at specific timings, as these recitations are not directed toward the structure of the apparatus, but rather are directed toward the manner in which the claimed apparatus is operated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 8, 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 2018/0288346) in view of Kondo (US 2013/0126710).
Consider claims 2 and 13, and as applied to claims 1 and 12 above, Yoshida et al. does not explicitly teach that the light detecting device is configured to execute a global shutter.
Kondo similarly teaches an array of pixels (50, figure 1), wherein each pixel (see figure 3) includes a photodiode (101), selection transistor (107) and amplification transistor (106), see paragraph 0096.
However, Kondo additionally teaches that each pixel (figure 3) further includes a discharge transistor (photoelectric conversion element reset transistor, 102) that discharges the charge accumulated in the photoelectric conversion unit (101) before exposure is started (“When the exposure of the global shutter system is performed, the vertical reading circuit 20 causes the photoelectric conversion elements 101 of all the unit pixels 50 to simultaneously start the photoelectric conversion by simultaneously outputting the reset pulse signals ϕFT1-xx of all the unit pixels 50.” paragraph 0109, see figure 3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the light detecting device taught by Yoshida et al. be configured to execute a global shutter as taught by Kondo for the benefit of improving image quality by preventing distortion (Kondo, paragraph 0007).
Consider claim 8, and as applied to claim 1 above, Yoshida et al. does not explicitly teach that the light detecting device has a layered structure, the layered structure includes: a first substrate, and a second substrate laminated to the first substrate, each of the first photodiode and the second photodiode is on the first substrate, and each of the first selection transistor and the second selection transistor is on the second substrate.
Kondo similarly teaches an array of pixels (50, figure 1), wherein each pixel (see figure 3) includes a photodiode (101), selection transistor (107) and amplification transistor (106), see paragraph 0096.
However, Kondo additionally teaches that the light detecting device has a layered structure, the layered structure includes: a first substrate (11, figure 3), and a second substrate (12, figure 3) laminated to the first substrate (“Thus, in the solid-state imaging device 100, the pixel units 11 and 12 connected to each other via the bumps are configured to form a lamination structure in the region of a pixel array unit 40 of the solid-state imaging device 100.” paragraph 0012) , each of the first photodiode (101) and the second photodiode (101) is on the first substrate (11, see figure 3), and each of the first selection transistor (107) and the second selection transistor (107) is on the second substrate (12, see figure 3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the light detecting device taught by Yoshida et al. comprise a layered structure as taught by Kondo for the benefit of decreasing a chip area of a substrate including the photoelectric conversion unit (Kondo, paragraph 0010).
Consider claim 10, and as applied to claim 1 above, Yoshida et al. does not explicitly teach that each of the first pixel unit and the second pixel unit further includes a discharge transistor.
Kondo similarly teaches an array of pixels (50, figure 1), wherein each pixel (see figure 3) includes a photodiode (101), selection transistor (107) and amplification transistor (106), see paragraph 0096.
However, Kondo additionally teaches that each pixel (figure 3) further includes a discharge transistor (photoelectric conversion element reset transistor, 102) that discharges the charge accumulated in the photoelectric conversion unit (101) before exposure is started (“When the exposure of the global shutter system is performed, the vertical reading circuit 20 causes the photoelectric conversion elements 101 of all the unit pixels 50 to simultaneously start the photoelectric conversion by simultaneously outputting the reset pulse signals ϕFT1-xx of all the unit pixels 50.” paragraph 0109, see figure 3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have each pixel taught by Yoshida et al. include a discharge transistor as taught by Kondo for the benefit of enabling global reset of a pixel array (Kondo, paragraph 0109), and thus improving image quality by preventing distortion (Kondo, paragraph 0007).
Claims 3-7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 2018/0288346) in view of Kikuchi et al. (WO 2016/136448). US 2018/0013412 is assumed to be a valid English translation of WO 2016/136448 and portions cited herein refer thereto.
Consider claim 3, and as applied to claim 1 above, Yoshida et al. does not explicitly teach that the AD converter further includes a first part and a second part, the first part of the AD converter is on a first substrate, and the second part of the AD converter is on a second substrate laminated to the first substrate.
Kikuchi et al. similarly teaches a light detecting device (see figure 33) comprising a plurality of pixels (41) connected to an AD converter (ADC, 42, paragraph 0343, see figures 2 and 33) comprising a comparator (comparison unit, 51, paragraphs 0097, 0098 and 0347).
However, Kikuchi et al. additionally teaches that the AD converter (see figure 33) further includes a first part (transistors, 81, 82, 85) and a second part (transistors 83, 84, 86), the first part (transistors, 81, 82, 85) of the AD converter is on a first substrate (upper substrate, 11A, paragraph 0343), and the second part (transistors 83, 84, 86) of the AD converter is on a second substrate (lower substrate, 11C, paragraph 0343) laminated to the first substrate (11A, i.e. layered and metallically bonded, paragraphs 0340 and 0341, figure 32).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the light detecting device taught by Yoshida et al. be configured in the manner taught by Kikuchi et al. for the benefit of enabling a determining speed of a comparator to be improved and power consumption to be reduced (Kikuchi et al., paragraph 0023).
Consider claim 4, and as applied to claim 3 above, Yoshida et al. does not explicitly teach that the first substrate and the second substrate are electrically connected via a metal bond.
Kikuchi et al. further teaches that the first substrate (11A) and the second substrate (11C) are electrically connected via a metal bond (“metallic bonding, such as Cu Cu”, paragraph 0341).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the light detecting device taught by Yoshida et al. be configured in the manner taught by Kikuchi et al. for the benefit of enabling a determining speed of a comparator to be improved and power consumption to be reduced (Kikuchi et al., paragraph 0023).
Consider claim 5, and as applied to claim 4 above, Yoshida et al. does not explicitly teach that the first substrate and the second substrate are electrically connected via a metal bond.
Kikuchi et al. further teaches that the first part (81, 82, 85) of the differential input circuit (61) and the second part (83, 84, 86) of the differential input circuit (61) are electrically connected via the metal bond (see figure 33, paragraphs 0343 and 0341).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the light detecting device taught by Yoshida et al. be configured in the manner taught by Kikuchi et al. for the benefit of enabling a determining speed of a comparator to be improved and power consumption to be reduced (Kikuchi et al., paragraph 0023).
Consider claim 6, and as applied to claim 3 above, Yoshida et al. does not explicitly teach that the first part of the AD converter includes a first input and a second input, the first input is coupled to each of the first pixel unit and the second pixel unit, and the second input is coupled to a digital to analog converter that controls a voltage of the reference signal.
Kikuchi et al. further teaches that the first part (81, 82, 85) of the differential input circuit (61) includes a first input (i.e. for receiving “SIG” in figure 2, paragraphs 0096-0099 and 0108, see figures 2, 3 and 33) and a second input (i.e. for receiving “REF” in figure 2, paragraphs 0098, 0099 and 0108, see figures 2, 3 and 33), the first input is coupled to the plurality pixels (i.e. via floating diffusion 175, figure 33, paragraph 0193), and the second input is coupled to a digital-to-analog converter (DAC, 25, figure 2) that controls a voltage of a reference signal (REF, see figures 2, 3 and 33, paragraphs 0088, 0098 and 0108).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the light detecting device taught by Yoshida et al. be configured in the manner taught by Kikuchi et al. for the benefit of enabling a determining speed of a comparator to be improved and power consumption to be reduced (Kikuchi et al., paragraph 0023).
Consider claim 7, and as applied to claim 6 above, Yoshida et al. further teaches that the first input of the first part corresponds to each of the first amplification transistor (Mpx) and the second amplification transistor (Mpx, see figure 1), and the second input of the first part corresponds to the first MOS transistor (M3, see figure 2, paragraph 0026).
Consider claim 15, and as applied to claim 12 above, Yoshida et al. does not explicitly teach that the light detecting device further includes: a first substrate; and a second substrate laminated to the first substrate, the AD converter further includes a first part and a second part, the first part of the AD converter is on the first substrate, the second part of the AD converter is on the second substrate, and the first part of the AD converter and the second part of the AD converter are electrically connected via a metal bond.
Kikuchi et al. similarly teaches a light detecting device (see figure 33) comprising a plurality of pixels (41) connected to an AD converter (ADC, 42, paragraph 0343, see figures 2 and 33) comprising a comparator (comparison unit, 51, paragraphs 0097, 0098 and 0347).
However, Kikuchi et al. additionally teaches that the light detecting device (figure 33) further includes:
a first substrate (upper substrate, 11A); and
a second substrate (lower substrate, 11C) laminated to the first substrate (11A, i.e. layered and metallically bonded, paragraphs 0340 and 0341, figure 32),
the AD converter further includes a first part (transistors, 81, 82, 85) and a second part (transistors 83, 84, 86), the first part (81, 82, 85) of the AD converter is on the first substrate (11A, see figure 33, paragraph 0343), the second part (83, 84, 86) of the AD converter is on the second substrate (11B, see figure 33, paragraph 0343), and the first part (81, 82, 85) of the AD converter and the second part (83, 84, 86) of the AD converter are electrically connected via a metal bond (“metallic bonding, such as Cu Cu”, paragraph 0341).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the light detecting device taught by Yoshida et al. be configured in the manner taught by Kikuchi et al. for the benefit of enabling a determining speed of a comparator to be improved and power consumption to be reduced (Kikuchi et al., paragraph 0023).
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 9 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12,149,852. This is a statutory double patenting rejection.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 10-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,149,852. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-8 and 10-15 are anticipated by claims 1-14 of US 12,149,852 as follows:
Consider claim 1, claim 1 of US 12,149,852 teaches (in parentheses):
A light detecting device, comprising: (A light detecting device, comprising:)
a first pixel unit that includes: (a first pixel unit that includes:)
a first photodiode; (a first photodiode;)
a first transfer transistor coupled to the first photodiode; (a first transfer transistor coupled to the first photodiode;)
a first amplification transistor having a gate terminal coupled to the first transfer transistor; (a first amplification transistor having a gate terminal coupled to the first transfer transistor;) and
a first selection transistor coupled to the first amplification transistor; (a first selection transistor coupled to the first amplification transistor;)
a second pixel unit that includes: (a second pixel unit that includes:)
a second photodiode; (a second photodiode;)
a second transfer transistor coupled to the second photodiode; (a second transfer transistor coupled to the second photodiode;)
a second amplification transistor having a gate terminal coupled to the second transfer transistor; (a second amplification transistor having a gate terminal coupled to the second transfer transistor) and
a second selection transistor coupled to the second amplification transistor; (a second selection transistor coupled to the second amplification transistor;) and
an analog to digital (AD) converter that includes a first metal oxide semiconductor (MOS) transistor to which a reference signal is input (an analog to digital (AD) converter that includes a first metal oxide semiconductor (MOS) transistor to which a reference signal is input),
wherein the first pixel unit and the second pixel unit share the AD converter (the first pixel unit and the second pixel unit share the AD converter),
each of the first transfer transistor and the second transfer transistor is configured to enter into an ON state at a first timing (each of the first transfer transistor and the second transfer transistor is configured to enter into an ON state at a first timing),
the first selection transistor is configured to enter into an ON state at a second timing (the first selection transistor is configured to enter into an ON state at a second timing), and
the second selection transistor is configured to enter into an ON state at a third timing (the second selection transistor is configured to enter into the ON state at a third timing).
Consider claim 2, claim 2 of US 12,149,852 teaches (in parentheses):
the light detecting device is configured to execute a global shutter (the light detecting device is configured to execute a global shutter).
Consider claim 3, claim 3 of US 12,149,852 teaches (in parentheses):
the AD converter further includes a first part and a second part, the first part of the AD converter is on a first substrate, and the second part of the AD converter is on a second substrate laminated to the first substrate (the AD converter further includes a first part and a second part, the first part of the AD converter is on a first substrate, and the second part of the AD converter is on a second substrate laminated to the first substrate).
Consider claim 4, claim 4 of US 12,149,852 teaches (in parentheses):
the first substrate and the second substrate are electrically connected via a metal bond (the first substrate and the second substrate are electrically connected via a metal bond).
Consider claim 5, claim 5 of US 12,149,852 teaches (in parentheses):
the first part of the AD converter and the second part of the AD converter are electrically connected via the metal bond (the first part of the AD converter and the second part of the AD converter are electrically connected via the metal bond).
Consider claim 6, claim 6 of US 12,149,852 teaches (in parentheses):
the first part of the AD converter includes a first input and a second input, the first input is coupled to each of the first pixel unit and the second pixel unit, and the second input is coupled to a digital to analog converter that controls a voltage of the reference signal (the first part of the AD converter includes a first input and a second input, the first input is coupled to each of the first pixel unit and the second pixel unit, and the second input is coupled to a digital to analog converter that controls a voltage of the reference signal).
Consider claim 7, claim 7 of US 12,149,852 teaches (in parentheses):
the first input of the first part corresponds to each of the first amplification transistor and the second amplification transistor, and the second input of the first part corresponds to the first MOS transistor (the first input of the first part corresponds to each of the first amplification transistor and the second amplification transistor, and the second input of the first part corresponds to the first MOS transistor).
Consider claim 8, claim 8 of US 12,149,852 teaches (in parentheses):
the light detecting device has a layered structure, the layered structure includes: a first substrate, and a second substrate laminated to the first substrate, each of the first photodiode and the second photodiode is on the first substrate, and each of the first selection transistor and the second selection transistor is on the second substrate (the light detecting device has a layered structure, the layered structure includes: a first substrate, and a second substrate laminated to the first substrate, each of the first photodiode and the second photodiode is on the first substrate, and each of the first selection transistor and the second selection transistor is on the second substrate).
Consider claim 10, claim 9 of US 12,149,852 teaches (in parentheses):
each of the first pixel unit and the second pixel unit further includes a discharge transistor (each of the first pixel unit and the second pixel unit further includes a discharge transistor).
Consider claim 11 claim 10 of US 12,149,852 teaches (in parentheses):
the second timing is subsequent to the first timing, and the third timing is subsequent to the second timing (the second timing is subsequent to the first timing, and the third timing is subsequent to the second timing).
Consider claim 12, claim 11 of US 12,149,852 teaches (in parentheses):
An electronic device, comprising: (An electronic device, comprising:)
a light detecting device including: (a light detecting device including:)
a first pixel unit that includes: (a first pixel unit that includes:)
a first photodiode; (a first photodiode;)
a first transfer transistor coupled to the first photodiode; (a first transfer transistor coupled to the first photodiode;)
a first amplification transistor having a gate terminal coupled to the first transfer transistor; (a first amplification transistor having a gate terminal coupled to the first transfer transistor;) and
a first selection transistor coupled to the first amplification transistor; (a first selection transistor coupled to the first amplification transistor;)
a second pixel unit that includes: (a second pixel unit that includes:)
a second photodiode; (a second photodiode;)
a second transfer transistor coupled to the second photodiode; (a second transfer transistor coupled to the second photodiode;)
a second amplification transistor having a gate terminal coupled to the second transfer transistor; (a second amplification transistor having a gate terminal coupled to the second transfer transistor) and
a second selection transistor coupled to the second amplification transistor; (a second selection transistor coupled to the second amplification transistor;) and
an analog to digital (AD) converter that includes a first metal oxide semiconductor (MOS) transistor to which a reference signal is input (an analog to digital (AD) converter that includes a first metal oxide semiconductor (MOS) transistor to which a reference signal is input),
wherein the first pixel unit and the second pixel unit share the AD converter (the first pixel unit and the second pixel unit share the AD converter),
each of the first transfer transistor and the second transfer transistor is configured to enter into an ON state at a first timing (each of the first transfer transistor and the second transfer transistor is configured to enter into an ON state at a first timing),
the first selection transistor is configured to enter into an ON state at a second timing (the first selection transistor is configured to enter into an ON state at a second timing), and
the second selection transistor is configured to enter into an ON state at a third timing (the second selection transistor is configured to enter into the ON state at a third timing).
Consider claim 13, claim 12 of US 12,149,852 teaches (in parentheses):
the light detecting device is configured to execute a global shutter (the light detecting device is configured to execute a global shutter).
Consider claim 14, claim 13 of US 12,149,852 teaches (in parentheses):
the second timing is subsequent to the first timing, and the third timing is subsequent to the second timing (the second timing is subsequent to the first timing, and the third timing is subsequent to the second timing).
Consider claim 15, claim 14 of US 12,149,852 teaches (in parentheses):
the light detecting device further includes: a first substrate; and a second substrate laminated to the first substrate, the AD converter further includes a first part and a second part, the first part of the AD converter is on the first substrate, the second part of the AD converter is on the second substrate, and the first part of the AD converter and the second part of the AD converter are electrically connected via a metal bond (the light detecting device further includes: a first substrate; and a second substrate laminated to the first substrate, the AD converter further includes a first part and a second part, the first part of the AD converter is on the first substrate, the second part of the AD converter is on the second substrate, and the first part of the AD converter and the second part of the AD converter are electrically connected via a metal bond).
Prior Art
Consider claim 9, and as applied to claim 1 above, Yoshida et al. further teaches that the AD converter includes:
a second MOS transistor (M5);
a third MOS transistor (M8);
a fourth MOS transistor (M7), wherein
a gate electrode of the third MOS transistor (M8) and a gate electrode of the fourth MOS transistor (M7) are connected to a drain of the first MOS transistor (M3, i.e. via C1, see figure 7),
a source of the first MOS transistor (M3) is connected to a drain of the second MOS transistor (M5, see figure 7),
However, the prior art of record does not teach nor reasonably suggest that a gate electrode of the third MOS transistor and a gate electrode of the fourth MOS transistor are connected to a drain of the third MOS transistor, wherein the first pixel unit and the second pixel unit are connected in parallel between the drain of the second MOS transistor and a drain of the fourth MOS transistor, in combination with the other elements recited in claims 1 and 9.
Conclusion
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637