DETAILED ACTION
Claims 1-13 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 6 is objected to because of the following informalities: The claim should end with a period “.” not a comma “,”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 7-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2:
This claim recites the limitation "the address" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 7:
This claim recites “request to read data” on line 5 and “data read request” on line 9. It is not clear to the reader if these are the same of different requests and, therefore, render this claim indefinite. Clarification and correction are required.
Claims 8-11:
These claims are also rejected because they depend on a base rejected claim and have the same problems of indefiniteness.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated Odlivak et al. (US-20080184072), hereinafter Odlivak.
Claim 1:
Odlivak teaches a semiconductor device (a functional block 100, which is shown in FIG. 1 and may be an integrated circuit (IC), ¶ [0028]) comprising:
a read only memory in which data is stored (A system in which firmware residing in ROM may be upgraded without re-spinning silicon, Abstract);
a non-volatile memory (non-volatile media such as EEPROM and Flash, or SRAM solutions, ¶ [0010]. A scratch-ROM (SROM), which may be a writable memory where the corresponding patched code may be stored, ¶ [0029] and Abstract) in which replacement data for at least part of the data is stored; and
a controller (See controller/microcontroller in ¶¶ [0027], [0048] and [0051].) that performs either reading the data from the read only memory or reading the replacement data from the non-volatile memory (If the flag is not set, the code may continue executing normally. If the flag is set, a function identifier may be placed into a global memory location, and an assembly language "jump" instruction may be executed, redirecting program control to a specified location in a volatile Scratch Read Only Memory (SROM) where the corresponding patched code may be stored, Abstract) in response to data read request from a processor (see addressing in ¶ [0046]).
Claims 7 and 12:
These claims recite similar limitation as claim 1 and are rejected as such.
Claims 2, 8 and 13:
Odlivak teaches a first address information indicating a storage address of the at least part of the data stored in the read only memory is stored in the non-volatile memory, wherein the controller reads the replacement data from the non-volatile memory when the address indicated by the data read request is the same as the storage address indicated by the first address information. (see addressing in ¶ [0046]).
Claims 3 and 9:
Odlivak teaches a programmable controller (See controller/microcontroller in ¶¶ [0027], [0048] and [0051].) that does not perform writing the replacement data in a first mode, and performs writing of the replacement data in a second mode, with respect to an area where the replacement data is stored in the non-volatile memory.
Claims 4 and 10:
Odlivak teaches a first jump destination information for jumping to a first area of the non-volatile memory is stored in the read only memory, a second destination information for jumping to the first jump destination information is stored in a second area of the non-volatile memory, when the controller reads the replacement data from the non-volatile memory, the processor accesses the first jump destination information by referring to the second jump destination information, and accesses the replacement data by referring to the first jump destination information, and reads the replacement data. (In one set of embodiments, the specialized software technique may include assigning a flag to each patchable function. The first statement of each function may check its associated flag and determine if patch code should be executed in place of the current function present in the firmware residing in the ROM. If the flag is not set, then the code may continue to execute normally. If the flag is set, then an identifier may be placed into a global memory location, and an assembly language "jump" instruction may be executed, redirecting program control to a predetermined location in the SROM. A "jump" instruction may be preferred to a "call" instruction, as a "call" instruction would typically add an additional return address to the program's stack, while a "jump" instruction will leave the stack intact. To support patching more than one function, a global identifier and a conditional statement may be configured at a given location in the SROM, to determine which patched function to execute. Another assembly language "jump" instruction may be executed to redirect program execution to the correct patched function, while the stack remains intact. (¶ [0019]). [T]he SROM implementations may include a one-bit flag assigned for each patchable function. The first statement of each function may check its associated flag and determine if patch code should be executed in place of its current function contained in the firmware code that resides in the ROM (such as the ROM in FHM block 124 shown in FIG. 1). If the flag is not set, then the code may continue executing normally. If the flag is set, then a function identifier may be placed into a global memory location, and an assembly language "jump" instruction may be executed, redirecting program control to a specified location in the SROM. If more than one function is patched, the global identifier may be used to determine which patched function to currently execute. When using an assembly language "jump" instruction to redirect control, the patched function may return normally to its calling function. (¶ [0031]).)
Claims 5 and 11:
Odlivak teaches a second address information indicating a storage address of the replacement data is stored in the first area, the processor accesses the second address information by referring to the first jump destination information and reads the replacement data by referring to the second address information. (see addressing in ¶ [0046]).
Claims 6:
Odlivak teaches the first area is not connected to the controller and the second area is connected to the controller (See Fig, 1 and discussion therein).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Davis (US-20090043957) teaches A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result, the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address. When address requests are received thereafter, CAM circuit 200 compares the address request to its stored direct addresses. If a match is found the paired emulation address is passed through multiplexer 201 instead of the direct address. As a result, the substitute or upgraded data in configurable memory 203 is output to data bus 205 in place of the old data. (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 04/16/2026
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