DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “initiating arrangement, evaluation arrangement and recognition arrangement configured to” in claim 17.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hartlieb et al (US 2013/0254600, hereinafter Hartlieb).
Regarding claim 12, Hartlieb discloses a method for recognizing errors in a communication system in the form of a LIN bus system (the bus can comprises a single transmission line, Para [0023], LIN bus, Para [0024]), the method comprising the following steps: initiating a transmission of at least one data packet by a primary appliance of the communication system to at least one secondary appliance of the communication system (a data signal may be transmitted from the master node, Para [0034] and is transmitted to the other ASICs, Para [0034-35], which are non-master nodes/circuits in the system); receiving at least one status message from a transmitter-receiver of the communication system (the final node is able to transmit a response data frame with bits corresponding to errors, Para [0045], master node receives the response data, Para [0066], since the master node is able to transmit and receive data it is obvious to one of ordinary skill it has a transmitter and receiver); evaluating the at least one received status message with regard to an error upon receipt of a response data packet in response to the at least one transmitted data packet and recognizing an error based on the evaluation (the bit position in the response frame corresponds to a predefined error type, Para [0046], errors can be short-circuit, open load, etc., Para [0045], the information is accessed by the microcontroller, Para [0066], information is obtained with regards to the detected errors, Para [0089] and detailed error analysis can be performed by the microcontroller, Para [0093]).
Regarding claim 13, Hartlieb discloses the method according to claim 12, wherein a plurality of secondary appliances are provided, at which the transmission of the at least one data packet is initiated, wherein the status message is specific for an individual and/or for an origin identifier of the secondary appliances, the recognition further including: recognizing an error-causing secondary appliance of the secondary appliances based on the status message (there are a plurality of other ASICs/nodes in the system, Fig. 1, information can be obtained to find which particular integrated circuit in the system an error has occurred, Para [0067], each bit position in the faulty node query response is used to identify the ASIC, where the error occurred, Para [0070]).
Regarding claim 14, Hartlieb discloses the method according to claim 13, wherein the recognition further includes: assigning the error to one of at least two or at least three error categories, wherein the error categories include at least one of the following: a short-circuit error, during which transmission by at least one of the secondary appliances is prevented by the fact that a transmission line of the communication system is connected to electrical ground, an error due to an open load, during which transmission by at least one of the secondary appliances is prevented by the fact that the transmission line of the communication system is interrupted, an operating error in one of the secondary appliances (there are multiple error types including open load and short circuit, Para [0045]).
Regarding claim 15, Hartlieb discloses the method according to claim 12, wherein the evaluation is carried out based on a predefined system specification of the communication system, and wherein the recognition further includes: recognizing a cause of an error based on a comparison of the status message with the system specification (there are predefined error types, where each bit position corresponds to a specific error, Para [0045], the bit is set to a predefined value to indicate an error or not, Para [0047], therefore the bits in the response message are compared to the predefined value to determine if there is an error or not).
Regarding claim 17, Hartlieb discloses a communication system in the form of a LIN bus system (the bus can comprises a single transmission line, Para [0023], LIN bus, Para [0024], system Fig. 1), comprising: a primary appliance; at least one secondary appliance; and a device configured to recognize errors in the communication system (master node, other ASIC/nodes and central microcontroller, Fig. 1), wherein the device comprises: an initiating arrangement configured to initiate a transmission of at least one data packet by the primary appliance to the at least one secondary appliance (a data signal may be transmitted from the master node, Para [0034] and is transmitted to the other ASICs, Para [0034-35], which are non-master nodes/circuits in the system); a receiving arrangement configured to receive at least one status message from a transmitter-receiver of the communication system (the final node is able to transmit a response data frame with bits corresponding to errors, Para [0045], master node receives the response data, Para [0066], since the master node is able to transmit and receive data it is obvious to one of ordinary skill it has a transmitter and receiver); an evaluation arrangement configured to evaluate the at least one received status message with regard to an error upon receipt of a response data packet in response to the at least one transmitted data packet, and a recognition arrangement configured to recognize an error based on the evaluation (the bit position in the response frame corresponds to a predefined error type, Para [0046], errors can be short-circuit, open load, etc., Para [0045], the information is accessed by the microcontroller, Para [0066], information is obtained with regards to the detected errors, Para [0089] and detailed error analysis can be performed by the microcontroller, Para [0093]).
Regarding claim 18, Hartlieb discloses the communication system according to claim 17, wherein the device and/or the transmitter-receiver is part of the primary appliance, wherein further transmitter-receivers of the at least one or more secondary appliances are provided, wherein the primary appliance is provided as a commander and the secondary appliance is provided as a responder of the communication system (since the master node and the other ASICs/nodes are able to transmit and receive data it is obvious to one of ordinary skill they has a transmitter and receiver, master node in Fig. 1 with secondary nodes that are able to transmit response frames).
Regarding claim 19, Hartlieb discloses a device for data processing, the device configured to recognize errors in a communication system in the form of a LIN bus system (the bus can comprises a single transmission line, Para [0023], LIN bus, Para [0024], device, Fig. 1), the device configured to: initiate a transmission of at least one data packet by a primary appliance of the communication system to at least one secondary appliance of the communication system (a data signal may be transmitted from the master node, Para [0034] and is transmitted to the other ASICs, Para [0034-35], which are non-master nodes/circuits in the system); receive at least one status message from a transmitter-receiver of the communication system (the final node is able to transmit a response data frame with bits corresponding to errors, Para [0045], master node receives the response data, Para [0066], since the master node is able to transmit and receive data it is obvious to one of ordinary skill it has a transmitter and receiver); evaluate the at least one received status message with regard to an error upon receipt of a response data packet in response to the at least one transmitted data packet; recognize an error based on the evaluation (the bit position in the response frame corresponds to a predefined error type, Para [0046], errors can be short-circuit, open load, etc., Para [0045], the information is accessed by the microcontroller, Para [0066], information is obtained with regards to the detected errors, Para [0089] and detailed error analysis can be performed by the microcontroller, Para [0093]).
Regarding claims 20, Hartlieb discloses a non-transitory computer-readable storage medium on which are stored commands for recognizing errors in a communication system in the form of a LIN bus system (the bus can comprises a single transmission line, Para [0023], LIN bus, Para [0024]), the commands, when executed by a computer, causing the computer to perform the following steps: initiating a transmission of at least one data packet by a primary appliance of the communication system to at least one secondary appliance of the communication system (a data signal may be transmitted from the master node, Para [0034] and is transmitted to the other ASICs, Para [0034-35], which are non-master nodes/circuits in the system); receiving at least one status message from a transmitter-receiver of the communication system (the final node is able to transmit a response data frame with bits corresponding to errors, Para [0045], master node receives the response data, Para [0066], since the master node is able to transmit and receive data it is obvious to one of ordinary skill it has a transmitter and receiver); evaluating the at least one received status message with regard to an error upon receipt of a response data packet in response to the at least one transmitted data packet; recognizing an error based on the evaluation (the bit position in the response frame corresponds to a predefined error type, Para [0046], errors can be short-circuit, open load, etc., Para [0045], the information is accessed by the microcontroller, Para [0066], information is obtained with regards to the detected errors, Para [0089] and detailed error analysis can be performed by the microcontroller, Para [0093]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hartlieb and in view of Law (US 2023/0326265, hereinafter Law).
Regarding claim 16, Hartlieb discloses the method according to claim 12, but not explicitly wherein during the evaluation, the at least one received status message is evaluated with regard to a failure to receive the response data packet. Law discloses monitoring traffic over a LIN connection, Para [0163] and transmitting a heartbeat signal to other cores but failing to receive a response and determining the original signal has failed, Para [0129], obvious determination that a response has been failed to have been received. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize the techniques taught by Law in the system of Hartlieb in order to further detect failures in the system by sending heartbeat packets, thereby detecting failures sooner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN CUNNINGHAM whose telephone number is (571) 272-1765. The examiner can normally be reached Monday through Thursday 7:30-18:00 (EST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Vu can be reached on (571) 272-3155. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEVIN M CUNNINGHAM/Primary Examiner, Art Unit 2461
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