DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 10/15/2024 for application number 18/915,876.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “locking information is at a first level” and “locking information is at a second level.” There is indefinite scope for these limitations in the claim. The “first” and “second levels” have no distinction relative to each other and do not have a limiting definition in the claim. “First level” will be interpreted as an inactive state and “second level” will be interpreted as an active state for the purposes of examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 2021/0141412 A1) in view of Ha (US 2016/0116934 A1).
Regarding claim 1, Jeon teaches a semiconductor system (Figure 1, Figure 14) comprising:
a memory to store data (memory 20, Figure 14);
a first master intellectual property (IP) block (master IP block 200, Figure 1) configured to generate a first wakeup signal (“The first channel management circuit transmits a first clock request … in response to a first intellectual property (IP) block clock request received from a first IP block.” Par 0007) [the master IP block sends a clock request, corresponding to a first wakeup signal];
a first bus block configured to generate a second wakeup signal while performing a wakeup operation in response to the first wakeup signal (“The channel management circuit 130 transmits the clock request (REQ) signal … to the clock control circuit 122 f … the clock control circuit 122 f waits until it receives an ACK signal from the parent before enabling the clock source 124 f.” par 0041 and “Next, the clock control circuit 122 f transmits a clock request (REQ) having a second logic value (e.g., a clock provision request) to the clock control circuit 122 e corresponding to its parent,” par 0042) [the first bus clock (circuit 122f) transmits second wakeup signal (REQ to its parent) while it is still in a pending state, waiting for a return signal to complete its own wakeup];
a second bus block configured to generate a third wakeup signal while performing the wakeup operation in response to the second wakeup signal (“The clock control circuit 122 e receives a REQ signal from … the clock control circuit 122 f” par 0032 and “Such an operation may be similarly performed on other clock control circuits 122 a, 122 b, 122 c, and 122 d” par 0038 and Figure 1) [the second bus block (circuit 122e) receives the second signal from its child (122f) and as part of the hardware handshake, generates the third wakeup signal to its own parent (122d) while waiting to be enabled].
However, Jeon does not explicitly teach a third bus block configured to perform data communication with the memory and perform the wakeup operation in response to the third wakeup signal.
In the analogous art, Ha teaches a third bus block configured to perform data communication with the memory and perform the wakeup operation in response to the third wakeup signal (“The memory interface 370 controls the overall operation of the memory device 390 and controls data exchange between a host and the memory device 390.” Par 0121 and “The clock circuit 10 may be implemented in … memory interface 370 in the SoC 300 in a distributed manner.” Par 0119 and “the at least one clock component … is configured to receive the turn-on request signal from a clock component at a lower node” par 0017 and Figures 7, 11) [the memory interface 370 (third bus block) controls data exchange while also housing the distributed clock circuit that is sequentially enabled to allow those operations to occur].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Jeon and Ha before him before the effective filing date of the claimed invention, to have modified Jeon to incorporate the teachings of Ha to include a third bus block to perform data communication with the memory to select a specific clock path and turn off components of unselected paths to reduce overall power consumption, avoid inconvenience of controlling all components of a clock path individually and change the clock signal more easily. (Ha, paragraph 133)
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ha and in further view of Kurian et al. (US 2020/0264691 A1).
Regarding claim 2, Jeon and Ha teach the semiconductor system of claim 1. However, Jeon and Ha do not explicitly teach wherein the first bus block includes a first bus configured to perform data communication with the first master IP block; and a first power management unit (PMU) configured to generate the second wakeup signal while performing the wakeup operation in response to the first wakeup signal, the second bus block includes a second bus configured to perform data communication with the first bus; and a second PMU configured to generate the third wakeup signal while performing the wakeup operation in response to the second wakeup signal, the third bus block includes a third bus configured to perform data communication with the second bus and the memory; and a third PMU configured to perform the wakeup operation in response to the third wakeup signal.
In the analogous art, Kurian teaches, wherein the first bus block (subsystem 102, Figure 1A) includes
a first bus configured to perform data communication with the first master IP block (“the subsystem 102 may comprise an interconnection fabric 110 [first bus] that may communicatively couple the main PMU 106 … and/or Input/Output (I/O) peripherals 118 [master IP block].” Par 0033); and
a first power management unit (PMU) configured to generate the second wakeup signal while performing the wakeup operation in response to the first wakeup signal (“Based on the wake-up events 170 [first wakeup signal], the main PMU 106 may transition the device 100 from a sleep state to an active state [wakeup operation] (e.g., may turn on one or more of the child PMUs 142 [second wakeup signal]” par 0039 and “ to transition the device to the regular active state, the main PMU 106 may, at 214, wake up one or more child PMUs 142 a, 142 b, etc.” par 0079) [the main subsystem (first bus block) has a fabric (first bus) for data communication with internal Ips, and its main PMU responds to a wakeup event (first signal) by initiating a state transition which enables the child PMUs (generating the second wakeup signal)],
the second bus block (subsystem 140 a, Figure 1A) includes
a second bus configured to perform data communication with the first bus (“the subsystem 140 a may comprise an interconnect fabric 141 [second bus] connecting … to the fabric 110 of the subsystem 102.” Par 0036); and
a second PMU configured to generate the third wakeup signal while performing the wakeup operation in response to the second wakeup signal (“upon receiving such a notification, the child PMU 140 a [second PMU] … may wake up one or more of these components [third wakeup signal]… (e.g., processor 150, memory 1152, etc.)” Par 0042 and “the child PMU 142 a … may also handle the dynamic frequency and voltage scaling for its corresponding subsystem … dependent on the device power state [performing wakeup operation].” Par 0048),
the third bus block (subsystem 140 b, Figures 1A and 1B) includes
a third bus configured to perform data communication with the second bus and the memory (“the subsystem 140 b may have structure that may be at least in part similar to the subsystem 140 a.” par 0034 and paragraph 36 and Figures 1A and 1B) [since both subsystems may be symmetrical, subsystem 140b contains its own internal fabric (third bus) that communicates with subsystem 140a’s fabric (second bus) and its local memory]; and
a third PMU (child PMU 142b, Figure 1A) configured to perform the wakeup operation in response to the third wakeup signal (“the device 100 may implement a hierarchical PMU architecture, e.g., where the full PMU functionality may be split into a main or root PMU (e.g., PMU 106) and one or more layers of child PMUs such as child PMUs 142 a, 142 b [third PMU]” par 0037 and “a transition from one active state to another active state (or from an active state to a sleep state) may be controlled by a child PMU 140” par 0067) [the child PMU 142b performs a wakeup transition in response to the hierarchical signal passed down from the parent PMU layers].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Jeon, Ha and Kurian before him before the effective filing date of the claimed invention, to have modified Jeon and Ha to incorporate the teachings of Kurian to integrate hierarchical PMUs with sequential bus wakeups to drastically reduce power consumption in system sleep state by only activating lightweight units while powering down complex management logic. (Kurian, paragraphs 37, 62)
Regarding claim 3, Jeon, Ha and Kurian teach the semiconductor system of claim 2. Kurian further teaches further comprising: a second master IP block (processor 150, Figure 1A) configured to generate a fourth wakeup signal and perform data communication with the second bus (“the subsystem 140 a may further comprise one or more processors 150… [and] an interconnect fabric 141 connecting various components” par 0036 and “the child PMU 142 a … may also service one or more power-related requests [fourth wakeup signal] from the components (e.g., handling requests from the CPUs or MCUs)” par 0048) [the processor 150 performs data communication via the interconnect fabric and generates power-related requests to the child PMU that triggers subsequent power state transitions],
wherein the second PMU is configured to generate a fifth wakeup signal while performing the wakeup operation in response to the fourth wakeup signal (“the child PMU 142 a … may also service one or more power-related requests [fourth wakeup signal] from the components (e.g., handling requests from the CPUs or MCUs)” par 0048 and “a child PMU 142 [second PMU] may be in charge of transitioning [wakeup operation] to a specialized second active power state (e.g., a high active state discussed in FIG. 2), requesting … power rails 192 to be selectively powered ON [fifth wakeup signal]” par 0052), and
the third PMU is configured to perform the wakeup operation in response to the fifth wakeup signal (“PMU functionality may be split into … one or more layers of child PMUs such as child PMUs 142 a, 142 b [third PMU]” par 0037 and “a transition from one active state to another active state … may be controlled by a child PMU 140.” Par 0067) [child PMU 142 a (second PMU) receives a CPU request (fourth signal) and generates a power rail request (fifth signal) while transitioning states, allowing child PMU 142b (third PMU) to performs its own hierarchical wakeup operation].
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ha and in further view of Kurian and Lee (US 2011/0283031 A1).
Regarding claim 4, Jeon, Ha and Kurian teach the semiconductor system of claim 2. However, Jeon, Ha and Kurian do not explicitly teach further comprising: a plurality of sub IP blocks; and an address decoder configured to generate an address wakeup signal based on address information of each of the plurality of sub IP blocks, wherein the first PMU includes a first hierarchical register configured to mask the second wakeup signal in response to the address wakeup signal.
In the analogous art, Lee teaches further comprising:
a plurality of sub IP blocks (IP blocks 111 to 113, Figure 1); and
an address decoder configured to generate an address wakeup signal based on address information of each of the plurality of sub IP blocks (“The bus 140 includes an address decoder 141 … The address decoder 141 is configured to decode address information included in a call signal.” Par 0043 and “the address decoder 141 decodes address information included in the call signal CS to select the first line La.” Par 0055) [the decoded address information corresponds to the address wakeup signal],
wherein the first PMU includes a first hierarchical register configured to mask the second wakeup signal in response to the address wakeup signal (“The default checking unit 142 may transfer the received call signal (or call information included in the call signal) to a slave IP block or the default slave IP block, depending upon the received decoded address information” par 0044 and “if the slave IP block to be called is judged to be inactivated, the procedure goes to step S240, in which the default checking unit 142/342 may sent the call signal (or call information included in the call signal) to a default slave IP block 150/350.” Par 0109 and “If a slave IP block to be called is judged to be inactive, the default checking unit 142 switches the call signal to the default slave IP block 150.” Par 0049 and “a call signal CS is not sent to the second and third IP block 112 and 113.” Par 0078) [the default checking unit corresponds to the hierarchical register by using the decoded address to block (mask) transmission of the call signal (second wakeup signal) to an inactive block and rerouting it to the default slave block].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Jeon, Ha, Kurian and Lee before him before the effective filing date of the claimed invention, to have modified Jeon, Ha and Kurian to incorporate the teachings of Lee to mask a wakeup signal in response to an address wakeup signal to increase the reliability of the SoC by ensuring the master IP block always receives an answer signal via the default slave IP block, preventing the system from hanging during power-saving transitions. (Lee, paragraph 0114)
Regarding claim 5, Jeon, Ha, Kurian and Lee teach the semiconductor system of claim 4. Lee further teaches wherein the second PMU includes a second hierarchical register configured to mask the third wakeup signal in response to the address wakeup signal (“The default checking unit 342 [second hierarchical register; the default checking unit contains individual logic gates acting as multiple registers needed to independently mask signals for different power domains] sends the call signal [third wakeup signal] to a slave IP block or a default slave IP block, depending upon decoded address information [address wakeup signal] and control signals indicating activation or inactivation of a power domain [second PMU control]” par 0094 and Figure 2).
Regarding claim 6, Jeon, Ha, Kurian and Lee teach the semiconductor system of claim 5. Lee further teaches wherein
the address decoder is configured to generate the address wakeup signal based on address information of a first sub IP block that performs data communication with the second bus block among the plurality of sub IP blocks (“The address decoder 141 is configured to decode address information included in a call signal. Address information in a call signal may be an address for designating a slave IP block [first sub bus block].” Par 0043 and “The address decoder 341 decodes address information included in the call signal. The address information may correspond to the fourth IP block 314… the second power domain 302 which includes the third and fourth IP blocks 313 and 314. The default checking unit 342 sends a call signal to the fourth IP block 314 or the default slave IP block 350, depending upon the decoded address information” Par 0095) [the address decoder generates the decoded selection signal (address wakeup signal) to identify a specific target sub IP block within the second power domain (corresponding to a second bus block)],
the first PMU (power control units within clock control part 120, Figure 2) is configured to generate the second wakeup signal by using the first hierarchical register that generates a high level signal in response to the address wakeup signal (“The address decoder 141 may decode address information decodes address information included in the call signal CS to select the first line La [address wakeup signal]. For example, the address decoder 141 selects the first line La by setting the first line La to a logic value ‘1’ ” par 0055 and “Since the first and third lines La and Lc are set to a logical value ‘1’, the second gate 162 [hierarchical register] outputs a logical value ‘1’ [high level signal]. As a result, when the second IP block is activated [second wakeup signal]” par 0065) [the first PMU’s activation signals (Lc) are combined with high-level address wakeup signal (La) in the internal gates to generate a high-level output that transmits the call signal (second wakeup signal) to the target IP block],
the second PMU (clock control units within clock control part 120, Figure 2) is configured to mask the third wakeup signal by using the second hierarchical register that generates a low level signal in response to the address wakeup signal (“Since the first line La [address wakeup signal] has a logical value ‘1’ and the third line Lc has a logical value ‘0’, the fifth line Le [output of hierarchical register] is set to a logical value ‘0’.” Par 0076 and “if the slave IP block to be called is judged to be inactivated, the procedure goes to step S240, in which the default checking unit 142/342 may sent the call signal (or call information included in the call signal) to a default slave IP block 150/350.” Par 0109 and “If a slave IP block to be called is judged to be inactive, the default checking unit 142 switches the call signal to the default slave IP block 150.” Par 0049 and “a call signal CS is not sent to the second and third IP block 112 and 113.” Par 0078) [the clock control signals cause the hierarchical register to generate a logical value 0 when address decoder chooses an inactive block, masking the third wakeup signal], and
the first sub IP block is configured to perform the wakeup operation in response to the address wakeup signal (“the second IP block 112 [first sub IP block] is supplied with call information [address wakeup signal] (not shown) … and then generates an answer signal [wakeup operation] in response thereto.” Par 0069) [the second IP block 112, which is a slave IP block, (first sub IP block) performs wakeup operation by generating and transmitting an answer signal back to the bus after receiving the call information triggered by the specific address signal selection].
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ha and in further view of Lee.
Regarding claim 7, Jeon and Ha teach the semiconductor system of claim 1. However, Jeon and Ha do not explicitly teach further comprising: a third master IP block configured to generate a sixth wakeup signal and perform data communication with the third bus block; a plurality of sub IP blocks; and an address decoder configured to generate an address wakeup signal based on address information of a specific sub IP block among the plurality of sub IP blocks, wherein the third bus block is configured to perform the wakeup operation in response to the sixth wakeup signal, and the specific sub IP block is configured to perform the wakeup operation in response to the address wakeup signal.
In the analogous art, Lee teaches further comprising:
a third master IP block configured to generate a sixth wakeup signal and perform data communication with the third bus block (“The third power domain 303 [third bus block] comprises the sixth and seventh IP blocks 315 [third master IP block] and 316.” Par 0038 and “a call signal [sixth wakeup signal] is sent to the bus 340 from a master IP block,” par 0093);
a plurality of sub IP blocks (IP blocks 111 to 113, Figure 1); and
an address decoder configured to generate an address wakeup signal based on address information of a specific sub IP block among the plurality of sub IP blocks (“The bus 140 includes an address decoder 141 … The address decoder 141 is configured to decode address information included in a call signal… Address information in a call signal may be an address for designating a slave IP block.” Par 0043 and “the address decoder 141 decodes address information included in the call signal CS to select the first line La…by setting the first line La to a logic value ‘1’” Par 0055) [the address decoder extracts target address data from a master’s call to determine a specific sub IP block among the plurality and generates a high logic selection signal (address wakeup signal) on a dedicated line to trigger the corresponding power domain logic],
wherein the third bus block is configured to perform the wakeup operation in response to the sixth wakeup signal (“When each of the first to third power domains 301 to 303 is supplied with a power and a clock, IP blocks in each of the first to third power domains 301 to 303 may be activated.” Par 0085 and “a call signal [sixth wakeup signal] is sent to the bus 340 from a master IP block,” par 0093) [the third power domain [third bus block] performs its wakeup operation by transitioning to an active state based on the call signal from the master IP block within that domain to enable data transfer], and
the specific sub IP block is configured to perform the wakeup operation in response to the address wakeup signal (“The default checking unit 342 sends a call signal to the fourth IP [specific sub IP block] block 314… depending upon the decoded address information [address wakeup signal]” par 0095 and “When each of the first to third power domains 301 to 303 is supplied with a power and a clock, IP blocks [including 314] in each of the first to third power domains 301 to 303 may be activated [perform wakeup operation].” Par 0085).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Jeon, Ha and Lee before him before the effective filing date of the claimed invention, to have modified Jeon and Ha to incorporate the teachings of Lee to integrate an address decoder and generate address wakeup signals to increase the reliability of the SoC by ensuring the master IP block always receives an answer signal via the default slave IP block, preventing the system from hanging during power-saving transitions. (Lee, paragraph 0114)
Regarding claim 8, Jeon, Ha and Lee teach the semiconductor system of claim 7, Lee further teaches
wherein the specific sub IP block is configured to perform data communication with the second bus block (“each of the first to sixth IP blocks 311 to 316 includes an interface (not shown) and is connected with the bus 340. The first to sixth IP blocks 311 to 316 exchange data with one another through the bus 340.” Par 0086) [the fourth IP block 314 is part of second power domain 302 (second bus block) and performs data communication via the system bus], and
the second bus block is configured to perform the wakeup operation in response to the address wakeup signal (“When each of the first to third power domains 301 to 303 is supplied with a power and a clock, IP blocks in each of the first to third power domains 301 to 303 may be activated.” Par 0085 and “It is assumed that a call signal on the fourth IP block 314 is provided to the bus 340 from the first IP block 311. The address decoder 341 decodes address information included in the call signal. The address information may correspond to the fourth IP block 314.” Par 0095 and Figure 5) [the second power domain performs its wakeup operation when the address decoder selects that domain using the decoded selection signal [address wakeup signal]].
Regarding claim 9, Jeon, Ha and Lee teach the semiconductor system of claim 7. Lee further teaches wherein
the second bus block (second power domain 302, Figure 5) includes
a second bus (bus 340, Figure 5); and
a second power management unit (PMU) configured to perform the wakeup operation in response to the address wakeup signal (“The first to sixth IP blocks 311 to 316 exchange data with one another through the bus 340.” Par 0086 and “The power and clock control part 120 generates control signals for activating or inactivating the first to third IP blocks 111 to 113.” Par 0031 and paragraphs 87-89 and Figure 5) [the second power domain 302 contains the third and fourth IP blocks; the second PMU (power and clock control part) performs the wakeup operation by supplying power and clock signals to activate the second bus block once the address decoder generates the high-level address wakeup signal targeting a block within that domain],
the third bus block (third power domain 303, Figure 5) includes
a third bus configured to perform data communication with the second bus and the third master IP block (“each of the first to sixth IP blocks 311 to 316 includes an interface (not shown) and is connected with the bus 340. The first to sixth IP blocks 311 to 316 exchange data with one another through the bus 340.” Par 0086 and Figure 5) [the third power domain contains the sixth and seventh IP blocks; the third master IP block corresponds to the IP block 315]; and
a third PMU configured to perform the wakeup operation in response to the sixth wakeup signal (“The first to sixth IP blocks 311 to 316 exchange data with one another through the bus 340.” Par 0089 and “a call signal is sent to the bus 340 from a master IP block,” par 0093) [the third PMU corresponds to the power and clock control units 325 and 326; the third PMU activates the domain to allow the master to initiate data communication via call signal (sixth wakeup call)], and
the specific sub IP block includes
a fourth bus configured to perform data communication with the second bus (“each of the first to sixth IP blocks 311 to 316 includes an interface (not shown) and is connected with the bus 340. The first to sixth IP blocks 311 to 316 exchange data with one another through the bus 340.” Par 0089) [the fourth bus corresponds to the interface included in the fourth IP block 314]; and
a fourth PMU configured to perform the wakeup operation in response to the address wakeup signal (“The default checking unit 342 sends a call signal to the fourth IP block 314 or the default slave IP block 350, depending upon the decoded address information” par 0095) [the fourth PMU corresponds to the default checking unit 342].
Claims 10-12, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Ha and in further view of Ichien et al. (US 2007/0150768 A1).
Regarding claim 10, Jeon and Ha teach the semiconductor system of claim 1. However, Jeon and Ha do not explicitly teach further comprising: a third master IP block configured to generate a sixth wakeup signal and perform data communication with the third bus block; and a first sub IP block configured to perform data communication with the third bus block, wherein the third bus block is configured to perform the wakeup operation in response to the sixth wakeup signal, and the third master IP block includes an interrupt request (IRQ) generator configured to transmit a seventh wakeup signal to the first sub IP block before generating the sixth wakeup signal.
In the analogous art, Ichien teaches further comprising:
a third master IP block configured to generate a sixth wakeup signal and perform data communication with the third bus block (“The interruption controller 10 [third master IP block], … are connected to the peripheral bus 33 [third bus block] respectively.” Par 0053 and “The interruption controller 10 … outputs the interruption signal IRQ [sixth wakeup signal] to the CPU 2.” Par 0058 and Figure 1); and
a first sub IP block configured to perform data communication with the third bus block (“The internal bus 31 [connected to CPU 2, the first sub IP block] can interface with the peripheral buses 32 and 33 [third bus block] through the bus controller 7.” Par 0054),
wherein the third bus block is configured to perform the wakeup operation in response to the sixth wakeup signal (“The interruption controller 10 [third master IP block], … are connected to the peripheral bus 33 [third bus block] respectively.” Par 0053 and “The interruption controller 10 … outputs the interruption signal IRQ [sixth wakeup signal] to the CPU 2.” Par 0058 and “the CPU 2 recognizes the state changes from standby to active with the interruption signal IRQ.” Par 0072 and Figure 1) [the peripheral bus performs it wakeup operation by transitioning to an active state once the IRQ signal is send to trigger system’s transition to idle mode], and
the third master IP block includes an interrupt request (IRQ) generator configured to transmit a seventh wakeup signal to the first sub IP block before generating the sixth wakeup signal (“the controller 10 asserts the interruption signal IRQ [seventh wakeup signal] to the CPU 2.” Par 0070 and “the CPU 2 recognizes the state changes from standby to active with the interruption signal IRQ.” Par 0072 and Figure 5) [the interrupt controller (IRQ generator) transmits the interruption signal as the seventh wakeup signal to start standby transition at time t3 which occurs before it generates the IRQ signal again as the sixth wakeup signal to notify the CPU that the wakeup operation to the active state is complete].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Jeon, Ha and Ichien before him before the effective filing date of the claimed invention, to have modified Jeon and Ha to incorporate the teachings of Ichien to integrate an interrupt request controller to reduce system power consumption in the standby state. (Ichien, paragraph 73)
Regarding claim 11, Jeon, Ha and Ichien teach the semiconductor system of claim 10. Ichien further teaches further comprising: a system controller configured to perform a locking setting operation or an unlocking operation on the first sub IP block (“the system controller 13 asserts a suspend interruption request signal IRstb [locking operation] to the interruption controller 10” par 0070 and “the system controller 13 asserts the interruption request signal IRact [unlocking operation] to the interruption controller 10, thereby the CPU 2 [first sub IP block] recognizes the state changes from standby to active” par 0072) [the system controller performs the locking (standby) and unlocking (active) operations on the CPU by managing specific transition interrupt request signals and system state changes],
wherein the IRQ generator is configured to transmit a control signal to the first sub IP block and control the system controller in response to the control signal (“The interruption controller 10 [IRQ generator] … outputs the interruption signal IRQ [control signal] to the CPU 2.” Par 0058 and “ the CPU 2 sets the standby flag (not shown) and asserts the standby signal STB to the system controller 13” par 0070) [the interruption controller transmits the IRQ control signal to the CPU which controls the system controller by asserting the STB signal to start the next phase of the power management sequence].
Claim 18 corresponds to claim 11 and is rejected accordingly.
Regarding claim 12, Jeon, Ha and Ichien teach the semiconductor system of claim 11. Ichien further teaches wherein
the first sub IP block is configured to transmit locking information to the system controller in response to the control signal (“The interruption controller 10 … outputs the interruption signal IRQ [control signal] to the CPU 2.” Par 0058 and “The CPU 2, after completing the instruction execution for the current processing … executes a CPU 2 standby instruction … asserts the standby signal STB to the system controller 13.” par 0070) [the CPU transmits the standby signal to the system controller in response to processing the interruption signal during to the transition to the standby mode],
the system controller is configured to
perform the unlocking operation on the first sub IP block when the locking information is at a first level (“The system controller 13, after detecting that those voltages are stabilized [locking information at a first level] in the power supply circuit 9, negates the clock control signal CKC to instruct the clock generation circuit 8 to restart the oscillation [unlocking operation]” par 0072) [the first level maps to the negated/inactive state (shown by voltage stabilization) which triggers the controller to restart the clock], and
perform the lock setting operation on the first sub IP block when the locking information is at a second level (“the CPU 2 … asserts the standby signal STB [locking information at a second level] to the system controller 13. The system controller 13 then asserts the clock control signal CKC and instructs the clock generation circuit 8 to stop the clock generation [lock setting operation].” Par 0070) [the second level maps to the active state of the standby signal STB which triggers the controller to stop the clock].
Claims 14, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ichien in view of Shon et al. (US 2019/0214989 A1).
Regarding claim 14, Ichien teaches the semiconductor system of claim 13. However, Ichien does not explicitly teach wherein the third level bus block includes a third level power management unit (PMU) configured to generate a first wakeup signal while performing the wakeup operation, the second level bus block includes a second level PMU configured to generate a second wakeup signal while performing the wakeup operation in response to the first wakeup signal, and the first level bus block includes a first level PMU configured to perform the wakeup operation in response to the second wakeup signal.
In the analogous art, Shon teaches wherein
the third level bus block includes a third level power management unit (PMU) configured to generate a first wakeup signal while performing the wakeup operation (“The clock control circuit 122 a [third level PMU] enables the clock source 124 a (for example, a multiplexing circuit) and transmits an acknowledgement ACK [first wakeup signal] to the clock control circuit 122 b.” par 0041),
the second level bus block includes a second level PMU configured to generate a second wakeup signal while performing the wakeup operation in response to the first wakeup signal (“the clock control circuit 122 e [second level PMU] transmits an acknowledgement ACK [second wakeup signal], providing a notification that provisioning of the clock has resumed … to the clock control circuit 122 f.” par 0041), and
the first level bus block includes a first level PMU configured to perform the wakeup operation in response to the second wakeup signal (“The clock control circuit 122 f [first level PMU] having received the acknowledgement ACK [second wakeup signal] enables the clock source 124 f to provide a clock signal to the IP block 200” par 0041).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ichien and Shon before him before the effective filing date of the claimed invention, to have modified Ichien to incorporate the teachings of Shon to integrate a hierarchical structure of clock control circuits to perform clock gating to allow for precisely and rapidly reducing power consumption. (Shon, paragraph 122)
Regarding claim 19, Ichien teaches an operating method of a semiconductor system comprising bus blocks and a plurality of intellectual property (IP) blocks (“The data processor 1 comprises a central processing unit (CPU) 2, … a flash memory 4 [IP blocks]” par 0052 and “The CPU 2, the DMAC 3, the flash memory 4, the RAM 5, and the bus controller are connected to an internal bus 31 respectively… The internal bus 31 interfaces to a peripheral bus 32 and another peripheral bus 33 ” Par 0053 and Figure 1), the operating method comprising.
However, Ichien does not explicitly teach transmitting a first wakeup signal to a second bus block that performs data communication with a first bus block among the bus blocks, while performing a wakeup operation on the first bus block; transmitting a second wakeup signal to a third bus block that performs data communication with the second bus block, while performing the wakeup operation on the second bus block in response to the first wakeup signal; performing the wakeup operation on the third bus block in response to the second wakeup signal, wherein the second bus block is a bus block of a higher level than the first bus block, and the third bus block is a bus block of a higher level than the second bus block.
In the analogous art, Shon teaches transmitting a first wakeup signal to a second bus block that performs data communication with a first bus block among the bus blocks, while performing a wakeup operation on the first bus block (“The channel management circuit 130 [first bus block] transmits a clock request REQ [first wakeup signal] having a second logic value … to the clock control circuit 122 f [second bus block]” par 0039 and “ the IP block 200 [on the first bus block] enters a running state from a sleep state [performing a wakeup operation]” par 0038);
transmitting a second wakeup signal to a third bus block that performs data communication with the second bus block, while performing the wakeup operation on the second bus block in response to the first wakeup signal (“The channel management circuit 130 [first bus block] transmits a clock request REQ [first wakeup signal] having a second logic value … to the clock control circuit 122 f [second bus block] … The clock control circuit 122 f cannot directly enable the clock source 124 f … and wait for the provision of clock signals from the parent.” par 0039 and “Next, the clock control circuit 122 f transmits a clock request REQ [second wakeup signal] … to the clock control circuit 122 e [third bus block] corresponding to its parent, and the clock control circuit 122 f waits for an acknowledgement ACK from the clock control circuit 122 e.” par 0040) [clock control circuit 122 f (second bus block) starts its wakeup process in response to a clock request (first wakeup signal) from its child by propagating a subsequent request (second wakeup signal) to its parent clock control circuit 122 e to secure the clock signal required for its own activation];
performing the wakeup operation on the third bus block in response to the second wakeup signal (“the clock control circuit 122 e transmits an acknowledgement ACK, providing a notification that provisioning of the clock has resumed from the clock source 124 e, to the clock control circuit 122 f.” par 0041 and paragraph 35 and Figure 1) [the clock control circuit 122 e (third bus block) starts its wakeup operation (resume clock provisioning) after receiving REQ (second wakeup signal) from the circuit 122 f],
wherein the second bus block is a bus block of a higher level than the first bus block (Figure 1, the clock management unit (first block) is at a first level from IP block 1 200 (a first level) and the second bus block (clock control circuit 122f) is above the clock management circuit; the circuit 122 f receives an REQ from the clock management circuit acting as a parent for the CM 130), and
the third bus block is a bus block of a higher level than the second bus block (Figure 1, clock control circuit 122 e (third block) is the parent of clock control circuit 122 f (second block); and paragraph 29).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ichien and Shon before him before the effective filing date of the claimed invention, to have modified Ichien to incorporate the teachings of Shon to integrate a hierarchical structure of clock control circuits to perform clock gating to allow for precisely and rapidly reducing power consumption. (Shon, paragraph 122)
Regarding claim 20, Ichien and Shon teach the operating method of claim 19. Ichien further teaches wherein the transmitting of the first wakeup signal includes masking the first wakeup signal when the wakeup operation on a first IP block that performs data communication with the first bus block among the plurality of IP blocks is performed (“The interruption controller 10 … to control both priority and masking in response to each inputted interruption signal and accepts the interruption request… The interruption request signal IRact is an interruption request signal for requesting the object to return to the active state from the standby state [wakeup state].” Par 0058) [the interruption controller 10 (acting as logic gate between bus levels) masks the transmission of the IRact signal (first wakeup signal) if the target CPU 2 (first IP block) on the internal bus 31 (first bus block) is already in the process of performing a wakeup operation].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ichien in view of Shon and in further view of Lee.
Regarding claim 15, Ichien and Shon teach the semiconductor system of claim 14. However, Ichien and Shon do not explicitly teach a plurality of sub intellectual property (IP) blocks; and an address decoder configured to generate an address wakeup signal based on address information of each of the plurality of sub IP blocks, wherein the third level PMU includes a hierarchical register configured to mask the first wakeup signal in response to the address wakeup signal.
In the analogous art, Lee teaches further comprising:
a plurality of sub intellectual property (IP) blocks (IP blocks 111 to 113, Figure 1); and
an address decoder configured to generate an address wakeup signal based on address information of each of the plurality of sub IP blocks (“The bus 140 includes an address decoder 141 … The address decoder 141 is configured to decode address information included in a call signal.” Par 0043 and “the address decoder 141 decodes address information included in the call signal CS to select the first line La.” Par 0055) [the decoded address information corresponds to the address wakeup signal],
wherein the third level PMU includes a hierarchical register configured to mask the first wakeup signal in response to the address wakeup signal (“The first to third power control units 121, 123, and 125 generate the first to third power control units PC1 to PC3, respectively.” Par 0032 and “Activation and inactivation of each of the first to third IP blocks 111 to 113 may be made according to corresponding control signals.” Par 0033 and “The default checking unit 142 [hierarchical register] may transfer the received call signal [first wakeup signal] (or call information included in the call signal) to a slave IP block or the default slave IP block [masking], depending upon the received decoded address information and control signals.” par 0044 and paragraph 9) [the third power control unit 125 (third level PMU) generates the PC3 control signal to activate/inactivate the third IP block 112 (slave IP block); the default checking unit masks (redirects) the call signal (first wakeup signal) in response to the decoded address information (address wakeup signal)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ichien, Shon and Lee before him before the effective filing date of the claimed invention, to have modified Ichien and Shon to incorporate the teachings of Lee to mask a wakeup signal in response to an address wakeup signal to increase the reliability of the SoC by ensuring the master IP block always receives an answer signal via the default slave IP block, preventing the system from hanging during power-saving transitions. (Lee, paragraph 0114)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ichien in view of Lee.
Regarding claim 16, Ichien teaches the semiconductor system of claim 13. Ichien further teaches a first level master intellectual property (IP) block configured to perform data communication with the first level bus block (“The CPU 2 [first level master IP block] and the DMAC 3 are bus master modules” par 0056 and Figure 1) [the CPU and DMAC are connected to the internal bus 31 (first level bus block)];
However, Ichien does not explicitly teach further comprising: a plurality of sub IP blocks; and an address decoder configured to generate an address wakeup signal based on address information of a specific sub IP block among the plurality of sub IP blocks, wherein the first level bus block is configured to perform the wakeup operation in response to the wakeup signal generated by the first level master IP block or the address wakeup signal, and the specific sub IP block is configured to perform the wakeup operation in response to the address wakeup signal.
In the analogous art, Lee teaches further comprising:
a plurality of sub IP blocks (IP blocks 111 to 113, Figure 1); and
an address decoder configured to generate an address wakeup signal based on address information of a specific sub IP block among the plurality of sub IP blocks (“The address decoder 141 is configured to decode address information included in a call signal [address wakeup signal]. Address information in a call signal may be an address for designating a slave IP block [specific sub IP block].” Par 0043) [the address decoder generates selective activation triggers (call signals) for specific slave IP blocks based on their unique decoded address information],
wherein the first level bus block is configured to perform the wakeup operation in response to the wakeup signal generated by the first level master IP block or the address wakeup signal (“When a call signal [master-generated wakeup signal] on the slave IP block is received from the master IP block [first level master IP block], the bus [first level bus block] is configured to transfer the received call signal [perform wakeup operation]” par 0008 and Figure 1), and
the specific sub IP block is configured to perform the wakeup operation in response to the address wakeup signal (“the slave IP block [specific sub IP block], which is called and activated, provides a response/answer signal to the bus 140/340 [in response to address wakeup signal].” Par 0110) [the bus initiates its wakeup/transfer operation upon receiving the call signal which then triggers the slave IP block to transition to an activated state and generate a response].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ichien and Lee before him before the effective filing date of the claimed invention, to have modified Ichien to incorporate the teachings of Lee to integrate an address decoder and have IP blocks perform wakeup operations based on the address wakeup signals to increase the reliability of the SoC by ensuring the master IP block always receives an answer signal via the default slave IP block, preventing the system from hanging during power-saving transitions. (Lee, paragraph 0114)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ichien in view of Kurian.
Regarding claim 17, Ichien teaches the semiconductor system of claim 13. Ichien further teaches a first level sub IP block configured to perform data communication with the first level bus block (“the flash memory 4 [first level sub IP block], … and the bus controller are connected to an internal bus 31 [first level bus block] respectively.” Par 0053).
However, Ichien does not explicitly teach further comprising: a first level master IP block configured to generate a fourth wakeup signal and perform data communication with the first level bus block; and wherein the first level bus block is configured to perform the wakeup operation in response to the fourth wakeup signal, and the first level master IP block includes an interrupt request (IRQ) generator configured to transmit a fifth wakeup signal to the first level sub IP block before generating the fourth wakeup signal.
In the analogous art, Kurian teaches further comprising:
a first level master IP block (subsystems 102 and 140a, Figure 1A) configured to generate a fourth wakeup signal and perform data communication with the first level bus block (“the subsystem 140 a [first level master IP block] may comprise an interconnect fabric 141 [first level bus] connecting various components of the subsystem 140 b [including the child PMU], and connecting to the fabric 110 of the subsystem 102.” Par 0036 and “a child PMU 142 may be in charge of transitioning to a specialized second active power state [fourth wakeup signal],” par 0052); and
wherein the first level bus block is configured to perform the wakeup operation in response to the fourth wakeup signal (“a child PMU 142 may be in charge of transitioning to a specialized second active power state [fourth wakeup signal], requesting (e.g., to the main PMU 106) power rails 192 to be selectively powered ON or OFF, optimizing operating conditions [performing wakeup operations]” par 0052), and
the first level master IP block includes an interrupt request (IRQ) generator configured to transmit a fifth wakeup signal to the first level sub IP block before generating the fourth wakeup signal (“one main Power Management Unit (PMU) 106 [IRQ generator] included in the AON subsystem 102.” Par 0029 and “a battery warning interrupt [fifth wakeup signal] may be generated by the main PMU 106” par 0056 and “the main PMU 106 may issue an interrupt warning to the child PMUs 140 [first level sub IP block],” par 0068 and “the main PMU 106 may then wake up the device 100 [fourth wakeup signal]” par 0056) [the main PMU transmits a battery warning interrupt to the child subsystems to pause tasks before subsequently generating the signal to wake up the device].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Ichien and Kurian before him before the effective filing date of the claimed invention, to have modified Ichien to incorporate the teachings of Kurian to integrate hierarchical PMUs with sequential bus wakeups to drastically reduce power consumption in system sleep state by only activating lightweight units while powering down complex management logic. (Kurian, paragraphs 37, 62)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ichien.
Regarding claim 13, Ichien teaches a semiconductor system (system of Figure 1) comprising:
a memory to store data (flash memory 4 and RAM 5, Figure 1);
a first level bus block (internal bus 31 (and connected components), Figure 1) configured to perform data communication with the memory [Figure 1, internal bus 31 is coupled to flash memory 4 and RAM 5];
a second level bus block (peripheral bus 32 (and connected components), Figure 1) configured to perform data communication with the first level bus block (“The internal bus 31 can interface with the peripheral buses 32” par 0054); and
a third level bus block (peripheral bus 33 (and connected components), Figure 1) configured to perform data communication with the second level bus block [Figure 1, the peripheral bus 33 communicates with the second level bus through the USB interface controller 16A and port 27 and memory card interface controller 15 and port 26],
wherein the first level bus block and the second level bus block are configured to perform a wakeup operation when the wakeup operation on the third level bus block is performed (“The system controller 13, after detecting that those voltages are stabilized in the power supply circuit 9, negates the clock control signal CKC to instruct the clock generation circuit 8 to restart the oscillation … thereby the CPU 2 recognizes the state changes from standby to active … the USB interface controller 16 … gets ready to start data communication ” par 0072) [the system controller, coupled to the third bus, performs a wakeup operation by restarting the system clock, which simultaneously triggers the first level bus block (containing the CPU) and the second level bus block (containing the USB controller) to transition from standby to an active state].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Baggett et al. (US 2020/0393891 A1) teaches an architecture for a device with a single pair of Ethernet in a multidrop bus topology that controls other devices in a network to operate in a sleep mode.
Henry et al. (US 2015/0067214 A1) teaches a microprocessor with multiple cores that are controls individually by a control unit and a clock signal. Each core carries out a sleep instruction and requests the control unit to put the core to sleep. After checking synchronization conditions, the control unit will wake up the last requesting core.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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