Prosecution Insights
Last updated: October 26, 2026
Application No. 18/916,068

STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE

Final Rejection §103
Filed
Oct 15, 2024
Priority
Feb 20, 2024 — RE 10-2024-0024486
Examiner
DARE, RYAN A
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
1y 6m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
449 granted / 592 resolved
+20.8% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
17 currently pending
Career history
620
Total Applications
across all art units

Statute-Specific Performance

§101
6.4%
-33.6% vs TC avg
§103
48.7%
+8.7% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 592 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The new title to the specification is accepted. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-7, 14-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chatterjee et al., US Patent 8,046,548, hereafter “Chatterjee,” in view of Jung, US PGPub 2020/00167095, further in view of Han et al., US PGPub 2023/0237021. With respect to claim 1, Chatterjee teaches a storage device comprising: a nonvolatile memory device (col. 6, lines 20-30, one of the disks, which may comprise non-volatile memories); and a controller comprising a plurality of counters, wherein the controller is configured to: increase a first count of a first counter among the plurality of counters based on first input/output (IO) requests received from an external host device (col. 14, line 34, through col. 15, line 11, and fig. 7, step 740, the I/O counter associated with the I/O request is incremented); and Chatterjee teaches to increase a second count of a second counter among the plurality of counters based on second IO requests received from the external host device (see fig. 3, I/O counter 330, which includes multiple I/O counters), but fails to teach that it occurs after a first flush request is received from the external host device. Jung teaches: increase a second count of a second counter based on second IO requests received from the external host device after a first flush request is received from the external host device (pars. 185-186 and fig. 11, the number of write requests are counted following a flush request from the host). Chatterjee and Jung fail to teach selecting a second counter among the plurality of counters, based on a first flush request being received from the external host device Han teaches: select a second counter among the plurality of counters, based on a first flush request being received from the external host device (pars. 39-41 and fig. 6, when the frozen FWS finishes flushing, subsequent I/O requests are directed to a second FWS with a second counter. Looking at fig. 6, if a flush request to FWS 320a completes, pointer 605 selects FWS 320b and associated counter 615b. Par. 34 discloses that requests are received from an external host). It would have been obvious to one of ordinary skill in the art, having the teachings of Chatterjee and Jung before him before the earliest effective filing date, to modify the storage system of Chatterjee with the storage system of Jung, in order to improve operational performance, as taught by Jung in par. 51. Further, it would have been obvious also having the teachings of Han before him before the earliest effective filing date, to modify the storage system of Chatterjee and Jung with the storage system of Han, in order to reduce memory required, have performance gains in flushing data, and have consistent deduplication across nodes in the storage system, as taught by Han in par. 22. With respect to claim 2, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the storage device of claim 1, wherein the controller is further configured to decrease the first count based on the nonvolatile memory device being accessed according to one first IO request among the first IO requests independent of the first flush request (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented). With respect to claim 3, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the storage device of claim 2, wherein the controller is further configured to decrease the second count, after the first flush request is received, based on the nonvolatile memory device being accessed according to one second IO request among the second IO requests (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented, which occurs after a flush request, shown in fig. 7A, step 730). With respect to claim 4, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the storage device of claim 3, wherein the controller is further configured to increase a third count of a third counter among the plurality of counters based on third IO requests being received from the external host device (col. 14, line 34, through col. 15, line 11, and fig. 7, step 740, the I/O counter associated with the I/O request is incremented. Fig. 3, I/O counter 330, includes multiple I/O counters, which includes a third counter). Chatterjee doesn’t teach that this occurs after a second flush request is received from the external host device. Jung teaches incrementing a counter after a second flush request is received from the external host device (pars. 185-186 and fig. 11, the number of write requests are counted following a flush request from the host). With respect to claim 5, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the storage device of claim 4, wherein the controller is further configured to: decrease the first count, independent of the first flush request and the second flush request, based on the nonvolatile memory device being accessed according to the one first IO request (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented); decrease the second count, after the first flush request is received and independent of the second flush request, based on the nonvolatile memory device being accessed according to the one second IO request (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented, which occurs after a flush request, shown in fig. 7A, step 730); and decrease the third count, after the second flush request is received, based on the nonvolatile memory device being accessed according to one third IO request among the third IO requests (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented, which occurs after a flush request, shown in fig. 7A, step 730. Fig. 3, I/O counter 330, includes multiple I/O counters, which includes a third counter). With respect to claim 6, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the storage device of claim 2, wherein the controller is configured to: generate an IO issue comprising a first index indicating the first counter based on the one first IO request (col. 14, line 34, through col. 15, line 17, and fig. 7, the I/O is issued, and has a corresponding counter for the I/O request); and decrease the first count based on the IO issue being completed (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented). With respect to claim 7, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the storage device of claim 1, wherein the controller is further configured to: manage a first bitmap comprising bits respectively corresponding to the plurality of counters (col. 10, line 64, through col. 11, line 7, the gate bitmap); set, based on the first flush request, a bit of the first bitmap corresponding to the first counter to a first value in response to the first count not being “0” (col. 10, line 64, through col. 11, line 7, the gate bit is set to a value when the I/O counter for the gate bit is not zero); and set, based on the first flush request, the bit of the first bitmap corresponding to the first counter to a second value in response to the first count being “0” (col. 10, line 64, through col. 11, line 7, when the I/O counter for the gate bit is zero, the gate bit is cleared). With respect to claim 14, Chatterjee, Jung and Han teach the limitations of the parent claim. Jung further teaches the storage device of claim 1, wherein the controller is further configured to: send, to the external host device, a response indicating that the first IO requests are completed after the first IO requests are buffered; and send, to the external host device, a response indicating that the second IO requests are completed after the second IO requests are buffered (pars. 184-189, the write operations are buffered in fig. 11, then the flush response is output to the host in fig. 12). With respect to claim 15, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the storage device of claim 1, wherein the controller is further configured to provide, based on a request of the external host device, information indicating a number of the plurality of counters to the external host device (col. 9, lines 29-39, the size of the gate bitmap is provided, which corresponds to information indicating a number of the plurality of counters, as the number of counters corresponds to the number of gate bits, as disclosed in col. 10, line 34, through col. 11, line 7). With respect to claim 16, Chatterjee teaches an operating method of a storage device which includes a nonvolatile memory device and a controller, the method comprising: receiving, at the controller, first input/output (IO) requests from an external host device (col. 14, lines 6-12, the I/O request is received from the initiator (host)); increasing, at the controller, a first count of a first counter based on the first IO requests (col. 15, lines 5-11, incrementing the I/O counter); decreasing, at the controller the first count based on the nonvolatile memory device being accessed according to at least one first IO request among the first IO requests (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented); and Chatterjee teaches increasing, at the controller, a second count of a second counter based on second IO requests being received from the external host device (see fig. 3, I/O counter 330, which includes multiple I/O counters), but fails to teach that it occurs after a first flush request is received. Jung teaches: increasing, at the controller, a second count of a second counter based on second IO requests being received from the external host device after a flush request is received (pars. 185-186 and fig. 11, the number of write requests are counted following a flush request from the host). Chatterjee and Jung fail to teach selecting a second counter among the plurality of counters, based on a first flush request being received from the external host device Han teaches: selecting, at the controller, a second counter based on a first flush request being received from the external host device (pars. 39-41 and fig. 6, when the frozen FWS finishes flushing, subsequent I/O requests are directed to a second FWS with a second counter. Looking at fig. 6, if a flush request to FWS 320a completes, pointer 605 selects FWS 320b and associated counter 615b. Par. 34 discloses that requests are received from an external host). It would have been obvious to one of ordinary skill in the art, having the teachings of Chatterjee and Jung before him before the earliest effective filing date, to modify the storage system of Chatterjee with the storage system of Jung, in order to improve operational performance, as taught by Jung in par. 51. Further, it would have been obvious also having the teachings of Han before him before the earliest effective filing date, to modify the storage system of Chatterjee and Jung with the storage system of Han, in order to reduce memory required, have performance gains in flushing data, and have consistent deduplication across nodes in the storage system, as taught by Han in par. 22. With respect to claim 17, Chatterjee, Jung and Han teach the limitations of the parent claim. Chatterjee further teaches the method of claim 16, wherein the controller includes a plurality of counters, the plurality of counters including the first counter and the second counter,wherein the controller is configured to manage a first bitmap including bits respectively corresponding to the plurality of counters (col. 10, line 64, through col. 11, line 7, the gate bitmap), and wherein the method further comprises, when the flush request is received: setting a bit of the first bitmap corresponding to the first counter to a first value based on the first count being greater than “0” (col. 10, line 64, through col. 11, line 7, the gate bit is set to a value when the I/O counter for the gate bit is not zero); and setting the bit of the first bitmap corresponding to the first counter to a second value based on the first count not being greater than “0” (col. 10, line 64, through col. 11, line 7, when the I/O counter for the gate bit is zero, the gate bit is cleared). With respect to claim 20, Chatterjee teaches a storage device comprising: a nonvolatile memory device; and a controller comprising a plurality of counters, wherein the controller is configured to: increase a first count of a first counter among the plurality of counters based on first input/output (IO) requests being received from an external host device (col. 14, line 34, through col. 15, line 11, and fig. 7, step 740, the I/O counter associated with the I/O request is incremented); decrease the first count, independent of the first flush request, based on the nonvolatile memory device being accessed according to one first IO request among the first IO requests (col. 15, lines 39-43 and fig. 7B, step 755, the I/O counter is decremented); manage a first bitmap comprising bits respectively corresponding to the plurality of counters (col. 10, line 64, through col. 11, line 7, the gate bitmap); set a bit of the first bitmap corresponding to the first counter to a first value based on the first flush request being received and the first count not being “0” (col. 10, line 64, through col. 11, line 7, the gate bit is set to a value when the I/O counter for the gate bit is not zero); and set the bit of the first bitmap corresponding to the first counter to a second value based on the first flush request being received and the first count being “0” (col. 10, line 64, through col. 11, line 7, when the I/O counter for the gate bit is zero, the gate bit is cleared). Chatterjee teaches to increase a second count of a second counter among the plurality of counters based on second IO requests being received from the external host device (see fig. 3, I/O counter 330, which includes multiple I/O counters), but fails to teach that it occurs after a first flush request is received from the external host device. Jung teaches: increase a second count of a second counter based on second IO requests being received from the external host device after a first flush request is received from the external host device (pars. 185-186 and fig. 11, the number of write requests are counted following a flush request from the host). Chatterjee and Jung fail to teach selecting a second counter among the plurality of counters, based on a first flush request being received from the external host device Han teaches: select a second counter among the plurality of counters, based on a first flush request being received from the external host device (pars. 39-41 and fig. 6, when the frozen FWS finishes flushing, subsequent I/O requests are directed to a second FWS with a second counter. Looking at fig. 6, if a flush request to FWS 320a completes, pointer 605 selects FWS 320b and associated counter 615b. Par. 34 discloses that requests are received from an external host). It would have been obvious to one of ordinary skill in the art, having the teachings of Chatterjee and Jung before him before the earliest effective filing date, to modify the storage system of Chatterjee with the storage system of Jung, in order to improve operational performance, as taught by Jung in par. 51. Further, it would have been obvious also having the teachings of Han before him before the earliest effective filing date, to modify the storage system of Chatterjee and Jung with the storage system of Han, in order to reduce memory required, have performance gains in flushing data, and have consistent deduplication across nodes in the storage system, as taught by Han in par. 22. Response to Arguments Applicant's arguments filed 07/20/2026 have been fully considered but they are not persuasive. The arguments are directed towards the cited Chatterjee and Jung failing to disclose the new limitation “select a second counter among the plurality of counters, based on a first flush request being received from the external host device.” These arguments are moot, as the new Han reference is supplied to teach this limitation. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN DARE/Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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Prosecution Timeline

Oct 15, 2024
Application Filed
Apr 21, 2026
Non-Final Rejection mailed — §103
Jun 12, 2026
Applicant Interview (Telephonic)
Jul 20, 2026
Response Filed
Oct 08, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
84%
With Interview (+8.2%)
3y 6m (~1y 6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 592 resolved cases by this examiner. Grant probability derived from career allowance rate.

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