DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group III, claims 11-20 in the reply filed on 02/24/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/24/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wheater; Donald L. (US 6073258 A hereafter referred to as Wheater), Sato; Tomotoshi (US 20070036010 A1, hereafter referred to as Sato) and Kim; So Hoe (US 20070174744 A1, hereafter referred to as Kim).
Rejection of claim 11:
Wheater explicitly discloses a semiconductor memory array containing primary address lines (word lines/bit lines) and redundant lines configured to replace defective elements (see Wheater, Abstract; Figs. 1-2). In addition, Wheater teaches a Built-In Self-Repair (BISR) or test logic wrapper 102 that evaluates localized array failures. Crucially, Wheater discloses monitoring the count/number of intersecting line or bit faults against a specific mathematical threshold criteria to determine an absolute "must-repair" or "need-to-repair" state (see Wheater, Col. 4, lines 7-67, "establishing a must-repair line when the count exceeds available spare resources").
Sato, in an analogous art, teaches a memory controller that continuously aggregates error-need metadata into an internal register/log while intentionally *withholding* physical address remapping during active runtime workloads and scheduling the deployment of collected repair-need data to coincide precisely with low-power or device idle states to minimize performance overhead (Sato, paragraphs [0117]-[0122] and Figure 12).
Alternatively Kim, in an analogous art, teaches scheduling the update of address-mapping registers to occur strictly within the mandatory background refresh command windows (Kim, Paragraphs [0019]-[0025]).It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the threshold-based, count-checking repair logic of Wheaterto incorporate the deferred data collection and scheduling mechanisms taught by Sato and/or Kim. An engineer reading Wheater would recognize that instantly acting on a "must-repair" count flag during high-speed CPU operations causes severe bus stalls. Incorporating Sato provides a clear, predictable method to collect that "need-to-repair" data in real-time but schedule the physical hardware remapping during a system idle state of (see Figure 16B). Alternatively, incorporating Kim allows the hardware to utilize existing, mandatory memory pause windows (like DRAM refresh cycles) to apply the repair-need info generated by Wheater's counting logic, thereby achieving a completely latency-free memory repair without degrading standard memory read/write cycles.
Rejection of claims 12-20:
Regarding dependent claims 12–20, the additional structural and functional limitations recited therein (including the storage of repair metadata, specific threshold evaluations, and timing parameters for deferred repair execution) are well-known, conventional design choices in the memory architecture art, as explicitly exemplified by the teachings of Wheater (Col. 4, lines 7–67) in view of Sato (¶¶ [0117]–[0122]) and Kim (¶¶ [0019]–[0025]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
1. US 2024/0006008 A1 (Park; Taewook et al. — Samsung Electronics)This document targets advanced Multi-Chip Package (MCP) and High Bandwidth Memory (HBM) architectures where memory dies are vertically stacked. It details a method where the memory device evaluates spatial error densities in real-time. Instead of executing an immediate hard-wired circuit swap, it caches the fail locations and delegates the mapping to a redundancy circuit based on host-driven command protocols or background diagnostic cycles. This represents a push to move the "repair analysis" infrastructure from an external factory tester directly onto the active controller logic of modern high-speed storage. It reinforces the idea that collecting repair information for later execution is a standard technique for multi-die stacked systems to prevent latency spikes during high-speed compute tasks.2. US 2022/0165351 A1 (Yang, Lei et al. — ChangXin Memory Technologies)This publication focuses heavily on optimizing **Built-In Redundancy Analysis (BIRA)** algorithms for dense DRAM layouts. It teaches an on-chip circuit that actively counts fail bits along individual word lines or bit lines. The core invention lies in how the state machine tracks these counts to establish a structural matrix, helping the chip decide whether to burn an entire spare row versus an individual spare column based on cluster thresholds.This is an excellent reference to establish that quantified bit-error counting is completely standard practice for competitive memory manufacturers. It proves that memory design engineers globally use localized failure tallies to triage hardware resources before committing to a hard physical line repair.3. US 2019/0237154 A1 (Choi; Kyung-Rak — Samsung Electronics)This earlier Samsung patent details an on-die Post-Package Repair (PPR) circuit layout. It explicitly describes a structure where the chip runs an autonomous memory test loop, identifies failing cell addresses, and updates an internal volatile/non-volatile "repair register." Critically, it describes storing this "repair information" dynamically and delaying the actual hard remapping step so that the memory cell swap doesn't clash with active read/write commands coming from the main processor.It provides the exact concept of *generating and holding repair-need metadata* in an internal lookup buffer to separate error detection from the actual physical repair execution loop.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112
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