Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. This office action is responsive to communication(s) filed on 7/9/2026.
2. Claims 1-20 are presented for examination.
3. Applicant's arguments with respect to the newly added limitations have been considered but have not been found persuasive. Therefore, all claims that are still rejected for the same reason as set forth in the previous Office action that are provided below for your convenience including the rejections of newly added limitations.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-2 and 7-18 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Castro US Pub. No. 20240303039 (previous cited).
As per claims 1, 10-11, 14 and 18, Figs. 15-21 and 31-32 and a paragraphs 354-356 of Castro are directed to a nonvolatile storage apparatus (15), comprising: a plurality of NAND strings (3102-3206, Fig. 32, par. 247), each NAND string formed of nonvolatile memory cells (3220, 3221 and 3224) that are vertically connected in series (Fig. 32); bit lines (1016 and 1018, par. 208) that extend horizontally in parallel (Fig. 18) and are connected to the plurality of NAND strings; and one or more control circuits (3104, Fig. 31, pars. 672) and 673) connected to the plurality of NAND strings and the bit lines, the one or more control circuits are configured to store weights (par. 673) in the nonvolatile memory cells, each individual weight stored (par. 149) by a group of two (Fig. 10) or more (Fig. 32), nonvolatile memory cells located in respective NAND strings that are each connected to different parallel bit lines (Fig. 10), which are electrically connected.
As per claim 2, the paragraphs 673 and 706 of Castro disclose wherein the one or more control circuits are configured to program each nonvolatile memory cell to three or more data states and an individual weight is represented by the combination of the states of at least a first nonvolatile memory cell and a second nonvolatile memory cell of the group.
As per claims 7 and 17, a paragraph 706 of Castro discloses wherein each nonvolatile memory cell is programmable to four data states, nonvolatile memory cells are configured as pairs of nonvolatile memory cells consisting of a first nonvolatile memory cell and a second nonvolatile memory cell, each individual weight stored by a combined data state of a pair of nonvolatile memory cells that is selected from seven combined data states.
As per claim 8, Figs. 31-32 and the paragraphs 672 and 685 of Castro disclose wherein each data state corresponds to a threshold voltage range (par. 189 or 192) and threshold voltage ranges of the four data states are unequally spaced apart.
As per claims 9 and 20, Fig. 1 and the paragraphs 81-82 of Castro disclose wherein the nonvolatile memory cells and the bit lines are located on a memory die (105) and the one or more control circuits are located on a control die (109) that is bonded to the memory die to form an integrated memory
As per claim 12, Fig. 11 and the paragraphs 214 and 225 of Castro disclose further comprising applying select voltages on select gates (1112-1115) corresponding to the plurality of nonvolatile memory cells ( 1106-1109) to provide an input vector for the vector-matrix multiplication operation.
As per claims 13 and 16, Fig. 32 and the paragraph 688 of Castro disclose further comprising applying read voltages on selected word lines coupled to the NAND strings and applying pass voltages (bypass voltage) on non-selected word lines coupled to the NAND strings to select the plurality of nonvolatile memory cells for vector-matrix multiplication.
As per claim 15, Fig. 19 of Castro discloses further comprising measuring current (3142) through two or more electrically connected bit lines (1830 and 1834) while a group of two or more NAND strings that are connected to the two or more electrically connected bit lines (Fig. 10 or 18) and that contain the two or more nonvolatile memory cells of the group are selected to obtain a combined current (1902) for the group of two or more nonvolatile memory cells.
Allowable Subject matter
7. Claims 19-20 are allowed.
8. Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9. The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having to wherein the first nonvolatile memory cell is located in a first NAND string connected to a first bit line and the second nonvolatile memory cell is located in a second NAND string connected to a second bit line that extends parallel to the first bit line and is physically connected to the first bit line in a claim 3; an odd numbered bit line (1018) that is physically connected to the even-numbered bit line in claims 5 and 19 and a combination of other limitations thereof as recited in claims.
Response to Arguments
10. Applicant's arguments with respect to the newly added limitations have been considered but are moot in view of the rejections as set forth in the rejection above.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
11. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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