Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
1. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: The office appreciate the applicant cleared the 112 first paragraph issue, however in independent claim 1, 8, 14, the office believe that it is not clear that which wordline or where does the third program voltage applied to? Is the third program voltage applied on a viticm wordline, an aggressor wordline, or some other wordlines? Please clarify.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-4, 6-10, 12-17, 19-20 are rejected under pre-AIA 35 U.S.C. 102(g) as being anticipated by Roohparvar et al (Pub. No.: US 2013/0201759).
5. Regarding independent claim 1, Roohparvar et al teaches a memory device (Fig. 1) including a plurality of memory cells (Fig. 2, #200) configured to store at least one bit (see Fig. 2, memory cells #208 for example is for data storage), the memory device (Fig. 1) comprising a first wordline (Fig. 2, #202N for example) and a second wordline (Fig. 2, the wordline below #202N for example), and configured to: perform a first programming operation (Fig. 10, #1001) on the first wordline (Fig. 2, #202N for example); perform a second programming operation (Fig. 10, #1003) on the second wordline (Fig. 2, the wordline below #202N for example); and perform a third programming operation (Fig. 10, #1005) with a voltage (Fig. 10, #1005, Final Vt with Fine programming) lower than (Fig. 10, paragraph [0059], lines 1-9) a voltage (Fig. 10, #1001, initial Vt with Coarse programming) of the first programming operation (Fig. 10, #1001), when the second programming operation (Fig. 10, #1003) is performed (see Fig. 10) after the first programming operation (Fig. 10, #1001) is performed (see Fig. 10).
6. Regarding claim 2, 15, Roohparvar et al teaches the first wordline (Fig. 2, #202N for example) is a victim wordline (Fig. 9, WL2 for example), and the second wordline (Fig. 2, the wordline below #202N for example) is an aggressor wordline (Fig. 9, WL1 for example).
7. Regarding claim 3, 9, 16, Roohparvar et al teaches when the plurality of memory cells (Fig. 2, #200) of the first wordline (Fig. 2, #202N for example) are in a lower state (Fig. 10, paragraph [0073]) and a plurality of memory cells (Fig. 2, #200) of the second wordline (Fig. 2, the wordline below #202N for example) are in a lower state (Fig. 10, paragraph [0073]), the lower state (Fig. 10, paragraph [0073]) referring to a state in which the plurality of memory cells (Fig. 2, #200) have threshold voltages below (see paragraph [0073], coarse voltage is lower than the fine voltage) the a particular voltage, the memory device (Fig. 1) is configured to perform a fifth programming operation (Fig. 10, #1009) on the second wordline (Fig. 2, the wordline below #202N for example) when a fourth programming operation (Fig. 10, #1007) is performed (see Fig. 10) on a third wordline (Fig. 2, the wordline below the second wordline for example) adjacent (Fig. 9 WL2, paragraph [0075]) to the second wordline (Fig. 2, the wordline below #202N for example).
8. Regarding claim 4, Roohparvar et al teaches when the plurality of memory cells (Fig. 2, #200) of the first wordline (Fig. 2, #202N for example) are in a lower state (Fig. 10, paragraph [0073]) and the plurality of memory cells (Fig. 2, #200) of the second wordline (Fig. 2, the wordline below #202N for example) are in a higher state (Fig. 10, paragraph [0073]), the lower state referring to a state in which the plurality of memory cells (Fig. 2, #200) have threshold voltages below (see paragraph [0073], coarse voltage is lower than the fine voltage) the a particular voltage, and the higher state referring to a state (Fig. 10, paragraph [0073]) in which the plurality of memory cells (Fig. 2, #200) have threshold voltages above (see paragraph [0073], coarse voltage is lower than the fine voltage) the particular voltage, the memory device (Fig. 1) is configured to stop an additional programming operation from being performed (see Fig. 10) on the first wordline (Fig. 2, #202N for example) after the third programming operation (Fig. 10, #1005).
9. Regarding claim 6, 12, 19, Roohparvar et al teaches the first wordline (Fig. 2, #202N for example) and the second wordline (Fig. 2, the wordline below #202N for example) are configured to include a quad level cell or triple level cell (see paragraph [0022]).
10. Regarding claim 7, 13, 20, Roohparvar et al teaches the first wordline (Fig. 2, #202N for example) is configured to perform the first programming operation (Fig. 10, #1001) using a voltage higher than (Fig. 10, Fine programing of Vt) a threshold voltage of a memory cell (Fig. 2, #208N).
11. Regarding independent claim 8, Roohparvar et al teaches an operating method of a memory device (Fig. 1) including a plurality of memory cells (Fig. 2, #200) each storing at least one bit, the operating method comprising: performing a first programming operation (Fig. 10, #1001) on memory cells (Fig. 2, #200) connected to a first wordline (Fig. 2, #202N for example), including applying a first voltage to the first wordline (Fig. 2, #202N for example); and performing a second programming operation (Fig. 10, #1003) on memory cells (Fig. 2, #200) connected to a second wordline (Fig. 2, the wordline below #202N for example) adjacent (Fig. 9 WL2, paragraph [0075]) to the first wordline (Fig. 2, #202N for example), including applying a second voltage to the second wordline (Fig. 2, the wordline below #202N for example), wherein, in the performing of the first programming operation (Fig. 10, #1001), the first programming operation (Fig. 10, #1001) is performed (see Fig. 10) on memory cells (Fig. 2, #200), and wherein when the second programming operation (Fig. 10, #1003) is performed (see Fig. 10) after the first programming operation (Fig. 10, #1001) is performed (see Fig. 10), a third programming operation (Fig. 10, #1005) is performed (see Fig. 10) on the memory cells (Fig. 2, #200) connected to the first wordline (Fig. 2, #202N for example), including applying a third voltage lower than (Fig. 10, paragraph [0059], lines 1-9) the first voltage to the first wordline (Fig. 2, #202N for example).
12. Regarding claim 10, 16, Roohparvar et al teaches when the memory cells (Fig. 2, #200) connected to the first wordline (Fig. 2, #202N for example) are in a lower state state (Fig. 10, paragraph [0073]), the lower state (Fig. 10, paragraph [0073]) referring to a state in which the memory cells (Fig. 2, #200) have a threshold voltage below (see paragraph [0073], coarse voltage is lower than the fine voltage) a particular voltage, and the memory cells (Fig. 2, #200) connected to the second wordline (Fig. 2, the wordline below #202N for example) are in the a higher state, the higher state referring to a state in which the memory cells (Fig. 2, #200) have a threshold voltage above (paragraph [0077]) the particular voltage, stopping a programming operation performed (see Fig. 10) after the third programming operation (Fig. 10, #1005).
13. Regarding independent claim 14, Roohparvar et al teaches a memory system (Fig. 1) including: a host configured to generate a re-program command (see Fig. 1, #124, Fig. 10, #1005 for re-programming from coarse to fine programming) for a wordline; and a memory device (Fig. 1) configured to receive the re-program command (see Fig. 1, #124, Fig. 10, #1005 for re-programming from coarse to fine programming), the memory device (Fig. 1) including a plurality of memory cells (Fig. 2, #200) each storing at least one bit (see Fig. 2, memory cells #208 for example is for data storage), and configured to perform a re-program operation (see Fig. 1, #124, Fig. 10, #1005 for re-programming from coarse to fine programming), wherein the memory device (Fig. 1) includes: a first wordline (Fig. 2, #202N for example) on which a first programming operation (Fig. 10, #1001) is configured to be performed (see Fig. 10); and a second wordline (Fig. 2, the wordline below #202N for example) on which a second programming operation (Fig. 10, #1003) is configured to be performed (see Fig. 10), wherein the memory device (Fig. 1) is configured to: perform the first programming operation (Fig. 10, #1001) on a memory cell (Fig. 2, #208N for example), and perform a third programming operation (Fig. 10, #1005) with a voltage (Fig. 10, #1005, Final Vt with Fine programming) lower than (Fig. 10, paragraph [0059], lines 1-9) a voltage (Fig. 10, #1001, initial Vt with Coarse programming) of the first programming operation (Fig. 10, #1001), when the second programming operation (Fig. 10, #1003) is performed (see Fig. 10) after the first programming operation (Fig. 10, #1001) is performed (see Fig. 10).
14. (Currently Amended) The memory system (Fig. 1) of claim 14, wherein, when a set of programmed memory cells (Fig. 2, #200) of the first wordline (Fig. 2, #202N for example) is in a lower state and a set of programmed memory cells (Fig. 2, #200) of the second wordline (Fig. 2, the wordline below #202N for example) are is in a lower state, the lower state referring to a state in which the set of programmed memory cells (Fig. 2, #200) have has a threshold voltage below the a particular voltage, the memory device (Fig. 1) is configured to perform a fifth programming operation (Fig. 10, #1009) when a fourth programming operation (Fig. 10, #1007) is performed (see Fig. 10) on a third wordline adjacent (Fig. 9 WL2, paragraph [0075]) to the second wordline (Fig. 2, the wordline below #202N for example).
Allowable Subject Matter
15. Claims 5, 11, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
16. With respect to claims 5, 11, 18, there is no teaching, suggestion, or motivation for combination in the prior art to when the plurality of memory cells of the first wordline are in a higher state, the higher state referring to a state in which the plurality of memory cells have threshold voltages above the a particular voltage, the memory device is configured to omit the third programming operation on the first wordline.
Conclusion
17. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, PARK (Pub. No: US 2026/0128106).
PARK (Pub. No: US 2026/0128106) shows aggressor word lines and victim word line.
18. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
10/06/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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