DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final Office Action in response to the communication filed on October 16, 2024.
Claims 1-12 have been examined.
Drawings
The drawings filed on October 16, 2024 are acceptable for examination proceedings.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in parent Application No. 18/916890, filed on October 16, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 16, 2024 was filed after the mailing date of the application 18/916890, filed on October 16, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Falik et al. (U.S. Patent Publication No.: US 7,398,554 Bl / or “Falik” hereinafter).
Regarding claim 1, Falik discloses “A semiconductor device comprising” (Fig. 1: a protected system 90 / a single chip i.e., a “semiconductor device”):
“a semiconductor chip on which a plurality of circuits are formed” (Fig. 1: a protected system 90 / a single chip i.e., a “semiconductor device”);
“wherein the plurality of circuits include a processor, a memory controller comprising a memory unit, a register unit, and a comparison circuit” (Fig. 1: a protected system 90 with Processor Core 120 i.e., a “processor”; Flash 110 i.e., a “memory”; and Fig. 2: Compare 218 a “comparison circuit”),
“a reset data transfer controller that executes data transfer from the memory unit to the register unit upon startup of the semiconductor chip, and” (Fig. 3: Steps 302-304; and Col 12:lines 9-14, a value of the lock word i.e., “data” is read from address 114 and stored in the first read register 212 i.e., “memory”; and Col 16: 19-24, the sampling/reading occurs after power up reset 504)
“a system controller that controls the processor, the memory controller, and the reset data transfer controller, wherein the memory unit comprises a first memory storing data necessary for the initial setting of the semiconductor chip” (Fig. 3: Step 306; and Col 12:lines 9-28, the lock word is stored),
“wherein the register unit comprises a first register referred to during the initial setting of the semiconductor chip and a second register for verifying the first register” (Fig. 3: Step 312; and Col 12:lines 12-28: “…Each reading of the value of the lock word is compared with a first reading stored in read register 212 by comparator 218 (step 312). The results of the comparisons are stored in logic circuitry. For example, it is assumed in the illustrated preferred embodiment that each result of the comparison is stored in a different flip flop 222, 228, ... 234 (step 314 for an equivalent comparison i.e. a match or step 316 for a non-equivalent comparison i.e. a non-match…”),
“wherein the reset data transfer controller executes data transfer N times, where N is an integer greater than or equal to 2, the reset data transfer controller transfers the data stored in the first memory to the first register at the first data transfer, and” (Fig. 3: Step 320; and Col 12:lines 29-34: “…The minimum number of readings (n) performed is two readings (mandating one flip flop), however in some preferred embodiments, more than two readings may be performed for additional security or for other consideration. For example, in a tested implementation of module 100, ten readings performed well….”)
“transfers the data stored in the first memory to the second register at the Nth data transfer, wherein the comparison circuit determines the match/mismatch between the data transferred to the first register and the data transferred to the second register and outputs a determination result signal representing the determination result to the system controller, and” (Col 12:lines 35-49: values are stored in different flip-flops)
“wherein the system controller, if the determination result signal indicates a match, starts the processor” (Fig. 3: Step 328; and Col 12:lines 62-67:”… If the comparison is positive (i.e. the first read value of the lock word equals the locking combination), lock 65 flag 182 is set. Considering that hack flag 188 is fed into "or" gate 240, lock flag 182 is also set if hacking flag 188 is set (step 328)…”),
“and if the determination result signal indicates a mismatch, causes the reset data transfer controller to execute the N times data transfer again” (Fig. 3: Step 330; and Col 12:lines 67-67”… Otherwise lock flag 182 is reset (step 330)…”).
Regarding claim 2, in view of claim 1, Falik discloses “wherein the system controller, after causing the reset data transfer controller to execute the N times data transfer again, starts the processor if the determination result signal indicates a match, semiconductor device” (Fig. 3: step 320; and Col 12:lines 29-34: “…The minimum number of readings (n) performed is two readings (mandating one flip flop), however in some preferred embodiments, more than two readings may be performed for additional security or for other consideration. For example, in a tested implementation of module 100, ten readings performed well….”).
Regarding claim 3, in view of claim 2, Falik discloses “wherein the reset data transfer controller comprises a random number generation circuit that generates the value of N as a random number each time the N times data transfer is executed” (Col 13: 23-27: a state machine provides values of n).
Regarding claim 4, in view of claim 2, Falik discloses “wherein the reset data transfer controller, if the value of N is an integer greater than or equal to 3, sequentially overwrites the data stored in the first memory to the second register from the second to the Nth data transfer” (Col 13: 53-65: “….For each lock word, comparison of the first reading of the value of each lock word with the corresponding locking combination 415 ... 4015 by comparators 406 ... 4006 generates 55 a separate locked/unlocked flag. Assuming m=3, as in FIG. 1, three locked/unlocked flags are generated: 182, 184, 186 corresponding to three sections of memory 110. A lock flag is set if a first reading of a corresponding lock word returns the same value as the locking combination of that lock word. All 60 lock flags (assuming m=3, lock flags 182, 184, 186) are also set if hacking flag 188 is set (step 328). If the first read value does not equal the corresponding locking combination and the hack flag is not set, then the corresponding lock flag is reset step 330”).
Regarding claim 5, in view of claim 1, Falik discloses “wherein the first memory is composed of a non-volatile memory that can be written only once” (Col 6: lines 41-42, non-volatile memory 110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Falik in view of Hwu et al. (U.S. Patent Publication No.: US 8271720 B1 / or “Hwu” hereinafter).
Regarding claim 6, Falik discloses “A semiconductor device comprising” (Fig. 1: a protected system 90 / a single chip i.e., a “semiconductor device”):
“a semiconductor chip on which a plurality of circuits are formed” (Fig. 1: a protected system 90 / a single chip i.e., a “semiconductor device”);
“wherein the plurality of circuits include a processor, a memory controller comprising a memory unit, a register unit, and a first comparison circuit” (Fig. 1: a protected system 90 with Processor Core 120 i.e., a “processor”; Flash 110 i.e., a “memory”; and Fig. 2: Compare 218 a “comparison circuit”),
“a reset data transfer controller comprising an ECC decoder and executing data transfer from the memory unit to the register unit via the ECC decoder upon startup of the semiconductor chip, and” (Fig. 3: Steps 302-304; and Col 12:lines 9-14, a value of the lock word i.e., “data” is read from address 114 and stored in the first read register 212 i.e., “memory”; and Col 16: 19-24, the sampling/reading occurs after power up reset 504)
“a system controller controlling the processor, the memory controller, and the reset data transfer controller, wherein the memory unit comprises a first memory storing data necessary for initial setting of the semiconductor chip” (Fig. 3: Step 306; and Col 12:lines 9-28, the lock word is stored),
wherein the register unit comprises a first register referred to during the initial setting of the semiconductor chip and a second register for verifying the first register” (Fig. 3: Step 312; and Col 12:lines 12-28: “…Each reading of the value of the lock word is compared with a first reading stored in read register 212 by comparator 218 (step 312). The results of the comparisons are stored in logic circuitry. For example, it is assumed in the illustrated preferred embodiment that each result of the comparison is stored in a different flip flop 222, 228, ... 234 (step 314 for an equivalent comparison i.e. a match or step 316 for a non-equivalent comparison i.e. a non-match…”),
“wherein the reset data transfer controller executes data transfer N times, where N is an integer greater than or equal to 2, the reset data transfer controller transfers the data stored in the first memory to the first register via the [ECC decoder] at the first data transfer, and” (Fig. 3: Step 320; and Col 12:lines 29-34: “…The minimum number of readings (n) performed is two readings (mandating one flip flop), however in some preferred embodiments, more than two readings may be performed for additional security or for other consideration. For example, in a tested implementation of module 100, ten readings performed well….”)
“transfers the data stored in the first memory to the second register via the [ECC decoder] at the Nth data transfer”(Col 12:lines 35-49: values are stored in different flip-flops),
[wherein the ECC decoder determines whether error correction is possible based on the error correction code added to the data, the ECC decoder transfers the data after error correction if error correction is possible, and outputs an ECC error signal to the system controller if error correction is not possible],
“wherein the first comparison circuit determines the match/mismatch between the data transferred to the first register and the data transferred to the second register, and outputs a determination result signal representing the determination result to the system controller, and wherein the system controller” (Fig. 3: Step 328; and Col 12:lines 62-67:”… If the comparison is positive (i.e. the first read value of the lock word equals the locking combination), lock 65 flag 182 is set. Considering that hack flag 188 is fed into "or" gate 240, lock flag 182 is also set if hacking flag 188 is set (step 328)…”),
“if the determination result signal represents a mismatch, causes the reset data transfer controller to execute the N times data transfer again” (Fig. 3: Step 330; and Col 12:lines 67-67”… Otherwise lock flag 182 is reset (step 330)…”),
“outputs a data recovery request for repairing the data stored in the first memory to the outside of the semiconductor chip upon receiving the [ECC error signal], and starts the processor if the determination result signal represents a match without inputting the [ECC error signal]” (Fig. 1: Module 92; and Col7: 24-28: data can be processed using Module 92; and 12:lines 62-67:”… If the comparison is positive (i.e. the first read value of the lock word equals the locking combination), lock 65 flag 182 is set. Considering that hack flag 188 is fed into "or" gate 240, lock flag 182 is also set if hacking flag 188 is set (step 328)…” ).
But Falik fails to specially disclose having an ECC decoder and determine if correction possible or not based on error correction code added to the data.
However, Hwu discloses (Hwu, Fig. 1: Error Correction Module 106; and Col 5: lines 15-20, decision is made to correct error using the ECC module before storing the data in the memory),
It would have been obvious to an ordinary person skilled in the art before the effective filing date of the claimed invention to employ the teachings of an ECC decoder and determine if correction possible or not based on error correction code added to the data of Hwu to the system of Falik to “…generate an error correction code for each portion of a data segment prior to storing the portion of the data segment in an addressable access unit…” (Hwu, Col 8:15-20) and the ordinary person skilled in the art would have been motivated to combine to “…instructs error correction management module 212 to perform error correction on a portion of a data segment that has been retrieved from an addressable access unit in association with a read command using the error correction code previously generated for the data segment…” (Hwu, Col 8:20-28).
Regarding claim 8, in view of claim 6, Falik discloses “wherein the system controller, after causing the reset data transfer controller to execute the N times data transfer again, starts the processor if the determination result signal represents a match without inputting the ECC error signal” (Fig. 3: Step 320; and Col 12:lines 29-34: “…The minimum number of readings (n) performed is two readings (mandating one flip flop), however in some preferred embodiments, more than two readings may be performed for additional security or for other consideration. For example, in a tested implementation of module 100, ten readings performed well….”) .
Regarding claim 9, in view of claim 8, Falik discloses “wherein the reset data transfer controller further comprises a random number generation circuit that generates a value of N as a random number each time the N times of data transfer are executed” (Col 13: 23-27: a state machine provides values of n).
Regarding claim 10, in view of claim 8, Falik discloses “wherein the reset data transfer controller, if the value of N is an integer greater than or equal to 3, sequentially overwrites the data stored in the first memory to the second register from the second to Nth data transfer” (Col 13: 53-65: “….For each lock word, comparison of the first reading of the value of each lock word with the corresponding locking combination 415 ... 4015 by comparators 406 ... 4006 generates 55 a separate locked/unlocked flag. Assuming m=3, as in FIG. 1, three locked/unlocked flags are generated: 182, 184, 186 corresponding to three sections of memory 110. A lock flag is set if a first reading of a corresponding lock word returns the same value as the locking combination of that lock word. All 60 lock flags (assuming m=3, lock flags 182, 184, 186) are also set if hacking flag 188 is set (step 328). If the first read value does not equal the corresponding locking combination and the hack flag is not set, then the corresponding lock flag is reset step 330”).
Regarding claim 11, in view of claim 6, Falik discloses “wherein the first memory is composed of a rewritable non-volatile memory” (Col 6: lines 41-42, non-volatile memory 110).
Regarding claim 12, in view of claim 7, Falik discloses “wherein the first memory is composed of a rewritable non-volatile memory, and the second memory is composed of a non-volatile memory that can be written only once” (Fig. 140 and 1110; and Col 6: lines 41-42, non-volatile memory 110).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Falik in view of Hwu and in further view of Minghui et al. (CN 114518972 A/ or “Minghui” hereinafter).
Regarding claim 7, in view of claim 6, Falik discloses sampling/reading occurs after power up reset (Falik, Col 16: 19-24).
Hwu disclose an ECC decoder and determine if correction possible or not based on error correction code added to the data (Hwu, Col 5: lines 1520).
But Falik and Hwu fail to specially disclose storing error recovery signal and making decision when a threshold number is reached.
However, Minghui discloses “wherein the system controller stores the number of recoveries performed in response to the data recovery request in the first memory” (Para 0123),
wherein the memory unit further comprises a second memory storing a preset upper limit of the recovery number” (Para 0124-0125),
wherein the reset data transfer controller further comprises a second comparison circuit determining whether the recovery number stored in the first memory has reached the upper limit stored in the second memory” (Para 0126),
“and outputs a recovery error signal to the system controller if the upper limit is reached, wherein the system controller controls so that at least the processor is not started upon receiving the recovery error signal” (Para 0139)
It would have been obvious to an ordinary person skilled in the art before the effective filing date of the claimed invention to employ the teachings of storing error recovery signal and making decision when a threshold number is reached of Minghui to the system of Falik and Hwu to have a system where a decision where to reset or restarting a memory device (Minghui, Para 141) and the ordinary person skilled in the art would have been motivated to combine to “…effectively prevent the recovery times from being too long or even deadlocking” (Minghui, Para 143).
Relevant Prior Arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 20240184735 A1) discloses :
[0015] Computing systems often include an integrated circuit with security circuitry and software to provide a measure of protection against defects, attacks, and other potentially compromising events. In today's computing environment, bad actors can attack computing devices at a myriad of levels using a multitude of attack vectors. For example, fault injection attacks reduce the protection many of these security paradigms afford. Fault injection attacks can bypass system security features, alter a system behavior to accomplish malicious intents, and/or uncover confidential information. Using a fault injection attack, an attacker can indirectly or directly alter programmed operations of an electronic component (e.g., a central processing unit) using glitches (e.g., sudden, temporary, injected faults in a system). Such an attack can sometimes “brick” a computing device, but in other instances, precise and targeted attacks can introduce compromising security threats. For example, fault injection attacks can allow adversaries to undermine the control flow of a program, which may result in an incorrect function getting called, such as in “return to libc” type attacks. In some cases, these attacks may cause the computing device to expose sensitive data or execute unverified code. Thus, fault injection attacks may alter a command or data being transferred within the computing system and can potentially alter execution flow of the system to cause downstream problems such as key leakage, privilege escalation, or unintentional execution of code.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDULLAH ALMAMUN whose telephone number is (571) 270-3392. The examiner can normally be reached on 8 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn Feild can be reached on (571) 272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABDULLAH ALMAMUN/Examiner, Art Unit 2431
/LYNN D FEILD/Supervisory Patent Examiner, Art Unit 2431