DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ju et al. KR 2021/0134494 A, hereinafter “Ju” in view of Belyansky et al. US 2019/0067078 A1, hereinafter “Belyansky”, further in view of Kim et al. US 2014/0001441 A1, hereinafter “Kim”.
Regarding independent claim 1, Ju discloses A method comprising: forming a shallow trench isolation region (Ju Fig 5 shallow trench isolation (STI) regions 255) aside of a protruding fin (Fig 5, fins 208A and 208B), wherein the protruding fin comprises a first semiconductor nanostructure and a second semiconductor nanostructure (alternating semiconductor layers 220 and 215);
forming a dielectric layer (oxide material 250 in Fig 5) on the shallow trench isolation region (deposited in region 255); forming a dummy gate stack over the protruding fin (Fig 12 dummy gate stack 280);
Ju does not disclose performing an implantation process to form a protection layer, wherein the protection layer covers the shallow trench isolation region.
However, in the same field of endeavor, Belyansky discloses performing an implantation process (Belyansky Fig 11 ions 114 are implanted into isolation material 108 [0064]) to form a protection layer (Fig 12 protective layer 116 is formed from the ion implantation [0067]), wherein the protection layer covers the shallow trench isolation region (Fig 12, the entire region of isolation including elements 108 and 116 between the protruding fins 104 are the STI regions [0050]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a semiconductor as disclosed in Ju, to include the method steps of Belyansky of the ion implantation to form a protection layer. It would be obvious to have Belyansky's method steps included in the process of Ju's method as shown in Ju Fig 5. The silicon liner layer, 240, in Ju Fig 5 creates the same structure as the protective liner 106 in Belyansky Fig 14; the STI dielectric region 250 (made of silicon oxide) in Ju may be the same as the STI isolation material 108 ("can be formed of various oxide or oxide-like materials" [0044]) of Belyansky Fig 14. Therefore, Ju may be modified, at the instance of Ju Fig 5, to include the ion implantation as disclosed in Belyansky, into the dielectric layer Ju Fig 5 layer 250, "to convert a portion of the oxide material into a different second material that defines a protective layer having a second material etch rate that is lower than the first material etch rate" [Belyansky 0005] this protects the device from "unintentional damage such as, for example, over-etching or pull-down" [Belyansky 0039].
Ju, modified to include the ion-implanted-protection layer as disclosed in Belyansky further discloses:
removing a sacrificial layer (Ju Fig 14, semiconductor layer 215 is laterally recessed) in the protruding fin (in fin structures 208A and 208B as labeled in Fig 12) to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure (Ju Fig 14, the removal of layer 215 leaves gaps 300A' and 300B' between layers 220);
removing the dummy gate stack (Ju removes dummy gate stack 280 in Fig 18 and replaces it with gate structure 290);
and forming a replacement gate stack (Ju Fig 18, 290), wherein a portion of the replacement gate stack is filled in the space (Ju Fig 25, gate electrode 374A, part of the gate stack is filled in the space between the nanostructures 220).
Neither Ju nor Belyansky disclose the steps of forming a disposable interposer in the space; and performing an etching process to remove the disposable interposer
However, in the same field of endeavor, Kim discloses a method of manufacturing a nanostructure semiconductor device with a protruding fin comprising a first semiconductor nanostructure and a second semiconductor nanostructure (Kim Fig 2A stack first nanowire stack 201 made of nanowire layer 206 and sacrificial material 222 [0033]), forming a space between the first and second semiconductor nanostructure (Kim Fig 2B, 211 is dimple volume openings between two adjacent nanowires 206 [0037]), and further discloses forming a disposable interposer in the space (Kim Fig 2C spacer material layer 226); performing an etching process to remove the disposable interposer (Kim [0043] dry or wet etch processes may be used by themselves or in combination “to remove a portion of spacer material 226 without removing spacer material 226 from dimple 211” shown in Fig 2E, this leftover spacer material forms inner spacers 202 (this follows the method as used by the instant application as well “disposable interposers 29 are laterally recessed to form inner spacers 44 (Fig 29B)” [instant 0106]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the methods as disclosed in Ju and Belyansky to include the additional step of depositing a disposable interposer in the space between the first and second semiconductor nanostructure to create internal spacers which “isolate the functional gate structure from the source/drain region” and “reduce overlap capacitance between the portions of gate electrode 216 internal to the nanowire stack and any adjacent conductive or semiconductive material within the source/drain region 212” [Kim 0049].
Regarding claim 2, Ju in view of Belyansky and Kim discloses The method of claim 1, wherein the etching process (etching process in claim 1 is what is used to etch the disposable interposer) is performed using an etching chemical (Kim inherently uses any chemical commonly known in the art for wet or dry etching), and wherein when the disposable interposer (disposable interposer from Kim Fig 2C sacrificial material 226 which is modified to be disposed around the channels 220’ in Ju Fig 23 then etched by an etching process as disclosed in Kim to create internal spacers between channels and adjacent nanowire stacks) is removed (Kim’s layer 226 is etched), the protection layer (Belyansky’s protection layer 116a Fig 14) separates the etching chemical (Kim discloses a wet or dry etching process to remove the sacrificial interposer 226 Kim Fig 2C; this inherently must use any chemical commonly known in the art for etching processes) from the shallow trench isolation region (Belyansky’s protection layer, modified to be implanted on the top of the STI regions of Jin Fig 5, regions 250, would serve to protect the STI regions during the etching of interposers which occurs in the manufacturing process around Jin Fig 12 when the formation of channel structures in the fins begins).
Regarding claim 3, Ju in view of Belyansky and Kim discloses The method of claim 1, wherein the dielectric layer (Ju Fig 12, dielectric layer 250) is deposited before the dummy gate stack is formed (layer 250 is deposited before the dummy gate stack 280 is formed), and wherein a portion of the dielectric layer (250) between the protruding fin (fin 208A) and a neighboring protruding fin (fin 208B) is implanted to form the protection layer (Ju modified with the ion-implantation as disclosed in Belyansky to create a protection layer on the upper surface of Ju Fig 12 layer 250).
Regarding claim 4, Ju in view of Belyansky and Kim discloses The method of claim 3, wherein the protection layer (Belyansky Fig 14 116a) further comprises a top portion of the shallow trench isolation region (Ju modified to add the protection layer 116a in the upper portion of the STI region in Ju Fig 12, STI 255, specifically dielectric layer 250).
Regarding claim 5, Ju in view of Belyansky and Kim discloses The method of claim 3, wherein the protection layer (Ju modified to have Belyansky’s protection layer 116a from Fig 14 on the upper portion of Ju Fig 12 layer 250) comprises a portion directly underlying the dummy gate stack (the upper surfaces of layer 250 is directly underlying the dummy gate stack 280 in Ju Fig 12).
Regarding claim 6, Ju in view of Belyansky and Kim discloses The method of claim 3, wherein after the replacement gate stack is formed (replacement gate structure Ju Fig 24 290, more specifically the gate electrode 374A of the gate stack), the protection layer (Belyansky’s protection layer on the upper surface of Ju Fig 24 layer 250) comprises a portion directly underlying the replacement gate stack (Ju Fig 24 upper surface of layer 250 is directly underlying replacement gate stack 374A and gate structure 290).
Regarding claim 7, Ju in view of Belyansky and Kim discloses The method of claim 1, wherein the dielectric layer comprises a gate spacer layer (Jin Fig 14 inner spacers 300A’ modified to be substituted by gate spacers disclosed in Kim Fig 2D-2E, formed by the etching of spacer layer, “spacer material 226” [Kim 0043], to form “self-aligned” [0041] internal spacers 202 shown in Kim Fig 2E), and the method further comprises: after the implantation process (Jin Fig 5 modified to add the ion implantation process as disclosed in Belyansky Fig 14), etching the gate spacer layer (Jin Fig 12-14 modified with the method of Kim, wherein instead of only removing the sacrificial semiconductor layer Jin 215 and to form inner spacers 300A’ in Jin Fig 14, adding the additional step of a disposable interposer from Kim Fig 2C spacer material layer 226 and etching that layer in modified Jin device Fig 12-14) to form gate spacers (Jin Fig 14 inner spacers 300A’ substituted with the gate spacers Kim discloses in Kim Fig 2D, internal spacers 202).
Regarding claim 9, Ju in view of Belyansky and Kim discloses The method of claim 1, wherein in the implantation process (Belyansky Fig 13, ions 114a being implanted), an element selected from the group consisting of silicon, carbon, nitrogen, helium, and combinations thereof is implanted (114a ions are silicon as disclosed by [Belyansky 0071]).
Regarding claim 10, Ju in view of Belyansky and Kim discloses The method of claim 9, wherein in the implantation process (Belyansky Fig 13), the element selected from the group consisting of carbon, nitrogen, and combinations thereof is implanted (114a ions are silicon [Belyansky 0071]).
Regarding claim 11, Ju in view of Belyansky and Kim discloses The method of claim 9, wherein in the implantation process (Belyansky Fig 13), silicon is implanted (114a ions are silicon [Belyansky 0071]).).
Regarding claim 12, Ju in view of Belyansky and Kim discloses The method of claim 1 further comprising, after the implantation process (Belyansky Fig 13-Fig 14), performing an anneal process (Belyansky Fig 17 shows “the semiconductor device 100 is illustrated undergoing a densification anneal of the first and second protective layers 116a and 116b”).
Therefore, , it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the step of annealing after the implantation process disclosed in Belyansky to the overall method as described by Ju to increase the density of the ion-implanted protection layers “such that the etch rate of the first and second protective layers 116a and 116b is decreased” providing increased etch selectivity for the device [Belyansky 0076].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ju in view of Belyansky and Kim, further in view of Zheng et al. CN 116598260 A, hereinafter “Zheng”.
Regarding claim 8, Ju in view of Belyansky and Kim discloses, The method of claim 1, but Jin, Kim, and Belyansky do not disclose the ordering of steps wherein during the implantation process, the dummy gate stack acts as an implantation mask to prevent a region directly underlying the dummy gate stack from being implanted.
However, in the same field of endeavor, Zheng discloses a method of manufacturing a gate structure comprising wherein during the implantation process (Zheng Fig 8 “in step 4, silicon ions are implanted on the first interlayer dielectric layer 107 by ion-implantation to form the second etch stop layer 108” [0054]), the dummy gate stack (Fig 8, dummy gate polysilicon layer 103) acts as an implantation mask to prevent a region directly underlying the dummy gate stack from being implanted (the dummy gate stack prevents the region below itself from being implanted with silicon ions during ion implantation; therefore, acting as an implantation mask).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to make the obvious modification of reordering the steps in the method of forming a semiconductor device as disclosed by the teachings of Jin, Belyansky, and Kim, to perform the ion implantation for the protection layer before the removal of the dummy gate, so that the dummy gate may act as a mask. Zheng discloses that using the dummy gates as masks while implanting silicon ions to form a protection layer is a known method which “improves the process window” [Zheng 0012].
The ordering of the method steps in claim 8 creates a species of the method, with claim 1 being generic. In the instant application, Figure 19 represents the first species of the generic method as claimed in claim 1, where the implantation happens before the dummy gates are formed, while Figure 34 represents the second species, as claimed in claim 8, where the implantation happens after the dummy gates are formed. These species of methods as disclosed in the instant application Fig 19 and Fig 34 both result in the same effect of forming a protection layer, and the reordering of the steps as disclosed in the instant and Zheng is an obvious change which yields predictable results and does not create an unexpected result of the claimed method (see MPEP 2144.04(IV)(C) “Changes in Sequences of Adding Ingredients”: In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results)).
Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ju in view of Belyansky.
Regarding independent claim 13, Ju discloses A structure comprising (Ju Fig 26): a semiconductor strip (strip of substrate protruding upwards, 206'); a first semiconductor nanostructure (channel structures 220') overlapping, and spaced apart from, the semiconductor strip (220' are overlapping and spaced apart and above the strip 206'); a shallow trench isolation region contacting an edge of the semiconductor strip (STI region 250 contacting the lateral edge of 206'); a gate stack (Ju Fig 26 metal gate 370A) comprising a first portion between the first semiconductor nanostructure and the semiconductor strip (the lower portion of 370A is between channels 220' and 206'), wherein the gate stack comprises a gate dielectric and a gate electrode over the gate dielectric (370A is made up of gate electrode 374A and gate dielectric 372); Ju does not disclose a protection layer between the shallow trench isolation region and the gate stack, wherein the protection layer comprises a dielectric material different from materials of the shallow trench isolation region and the gate dielectric.
However, in the same field of endeavor, Belyansky Fig 14 discloses a structure comprising a protection layer (first protective layer 116a Belyansky [0071]) between the shallow trench isolation region (between the STI region, Belyansky's isolating dielectric 108) and the gate stack (Belyansky does not disclose a gate stack, but the protective layer of Belyansky Fig 14 is obvious to include into the structure of Ju Fig 26 below the gate stack 370A), wherein the protection layer (Belyansky Fig 14 116a "The Si-rich protect layer 116a can be viewed as having higher levels of Si than the non-modified … 108" while a second ion-implantation process may further be performed, implanting a second type of ions such as nitrogen, helium, hydrogen, and argon [Belyansky 0071-0072]. This second ion-implantation creates the second protective layer 116b which may be disposed in the Ju Fig 26 structure.) comprises a dielectric material different from materials of the shallow trench isolation (Belyansky Fig 14 108 (silicon dioxide [Belyansky 0044]) and also Ju Fig 26 250 (silicon oxide [Ju 0022])) region and the gate dielectric (Ju Fig 26 gate dielectric 372, such as silicon dioxide [Ju 0051]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of semiconductor device as disclosed in Ju, to include the protective layer of Belyansky. Therefore, Ju may be modified, at the instance of Ju Fig 5, to include the ion implantation as disclosed in Belyansky, into the dielectric layer Ju Fig 5 layer 250, "to convert a portion of the oxide material into a different second material that defines a protective layer having a second material etch rate that is lower than the first material etch rate" [Belyansky 0005] this protects the device from "unintentional damage such as, for example, over-etching or pull-down" [Belyansky 0039].
Regarding claim 14, Ju in view of Belyansky discloses The structure of claim 13, wherein the shallow trench isolation region (Ju Fig 26 regions 255) comprises a dielectric liner (dielectric liner 235) and a dielectric region (250) over the dielectric liner (250 is disposed on 235), and wherein the protection layer (Ju modified to have the protection layer 116b from Belyansky Fig 18) contacts top surface of both of the dielectric liner and the dielectric region (Belyansky's protection layer would be disposed on the top surface of the dielectric region 250 in Ju Fig 26, in direct contact with region 250 and in contact with the top surface of 235 through 250).
Regarding claim 15, Ju in view of Belyansky discloses The structure of claim 13, wherein the protection layer comprises silicon oxynitride (Belyansky Fog 14-16 discloses "implantation of N ions into the Si-rich (SixOy) protective layer 116a forms an oxy-nitride SixOyNz) protective layer 116b" [0073]), and the shallow trench isolation region comprise silicon oxide (Ju's region 255, specifically 250 comprises silicon oxide [0022]).
Regarding claim 16, Ju in view of Belyansky discloses The structure of claim 13 further comprising a dielectric layer (Ju Fig 26 dielectric liner 235) between, and in contact with, the protection layer (Ju Fig 26 modified to have the protection layer 116b on the top surface of Ju Fig 26 250) and the semiconductor strip (Ju Fig 26 206'), wherein the dielectric layer comprises a different dielectric material than the protection layer (Belyansky's protection layer 116b comprises silicon oxynitride, while Ju's dielectric layer 235 comprises "oxygen and silicon such as SiO2" [Ju 0021]).
Regarding claim 17, Ju in view of Belyansky discloses The structure of claim 16, wherein the dielectric layer (Ju Fig 26 layer 250) comprises silicon oxide (comprises silicon oxide according to [Ju 0022]).
Regarding claim 18, Ju in view of Belyansky discloses The structure of claim 13 further comprising a source/drain region (Ju Fig 27a source/drain 310A and 310B) aside of the gate stack (aside of gate stack 370A as shown in Ju Fig 26), wherein the protection layer (protection layer of Belyansky 116b Fig 18 added to the structure of Ju Fig 27a on the upper surface of STI region 250) comprises a part directly under the source/drain region (the upper surface of Ju Fig 27a 250 is directly under the source/drain region; therefore, the modified structure of Ju and Belyansky comprises a part of the protective layer directly under the source/drain region).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ju in view of Belyansky.
Regarding independent claim 19, Ju discloses A structure (Ju Fig 26) comprising: a semiconductor substrate (Fig 26 206 and 206'); a shallow trench isolation region in the semiconductor substrate (255 regions including dielectric portions 250), wherein a portion of the semiconductor substrate is aside of and contacts the shallow trench isolation region to act as a semiconductor strip (206' clearly contacts the sides of the STI dielectric regions 250 in Fig 26); a semiconductor layer over the semiconductor strip (semiconductor channel layers 220'); a gate stack over (gate 370A) and encircling the semiconductor layer (gate electrode 374A encircles the semiconductor channel layers 220'); a source/drain region aside of the gate stack (Ju Fig 27a shows source/drain regions 310A and 310B on the lateral surface of the gate stack 370A);
Ju does not disclose a dielectric protection layer over the shallow trench isolation region, wherein the dielectric protection layer comprises a first portion directly underlying the gate stack, and a second portion directly underlying the source/drain region.
However, in the same field of endeavor, Belyansky discloses a dielectric protection layer (Belyansky Fig 18 116b) over the shallow trench isolation region (over isolation fill material 108).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Ju Fig 26 and 27a with the dielectric protection layer 116b of Belyansky Fig 18 over the shallow trench isolation region in Ju Fig 26, 250, so that the protection layer, made of a different material than the STI region can have etch selectivity and protect the STI region from over-etching [Belyansky 0039].
Ju as modified by the protection layer of Belyansky therefore discloses the limitation wherein the dielectric protection layer (Belyansky Fig 18 116b added onto the top surface of Ju Fig 26 dielectric region 250) comprises a first portion directly underlying the gate stack (upper surface of Ju 250 is directly underlying the gate structure 270A in Fig 26), and a second portion directly underlying the source/drain region (Ju Fig 27a also shows how the upper surface of Ju 250 is directly underlying the source/drain regions 310A and 310B, so the modified Ju structure would have the protection layer under the gate stack and source/drain regions).
Regarding claim 20, Ju in view of Belyansky discloses The structure of claim 19, wherein the dielectric protection layer (Belyansky 116b comprising SixOyNz) has a higher atomic percentage of an element (nitrogen) than the shallow trench isolation region (Ju's STI region 250 comprises silicon oxide [Ju 0022]), and wherein the element is selected from the group consisting of carbon, nitrogen, and combinations thereof (nitrogen [Belyansky 0073]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Reznicek et al. US 2019/0341316 A1 which discloses a method of forming a nanosheet FinFET comprising implanting nitrogen ions into a substrate to isolate source/drain regions in Figs 4-6.
Yang et al. US 2022/0173097 A1 which discloses a method of forming a nanostructure device comprising an isolation film, Fig 2C 112.
Jhan et al. US 2022/0344333 A1 which discloses a method of forming a field effect transistor comprising isolation structures between fin lattice structure, Fig 15A.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
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/TERESA N MICKEY/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
