DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujiyoshi (US 2014/0035601).
For claims 1 and 17, Figures 1 and 15 of Fujiyoshi (note that Figure 15 is a detail of Electrostatic Capacitance Detection Circuit 1 in Figure 1) teaches an analog circuit comprising: a signal input (Ain) configured to provide an input signal (Ain) via capacitive coupling (Cm, see Figure 1, note that Figure 15 is a detail of Electrostatic Capacitance Detection Circuit 1 in Figure 1), an edge detection stage (Csp, Csn, 24) operable to detect a rising edge and a falling edge of the input signal (Ain) provided at the signal input (Ain), an amplifier stage (11, Cfb, switches connected with Cfb, and Cds) with continuously variable gain and bandwidth, the amplifier stage (11, Cfb, switches connected with Cfb, and Cds) coupled between the signal input (Ain) and the edge detection stage (Csp, Csn, 24) and operable to amplify the input signal (Ain) provided by the signal input (Ain). Note that the indicator is shown in Figure 1 which includes an electrode (sensor electrode 2), an analog circuit (1) according to claim 1, and wherein the electrode is configured to receive the input signal via capacitive coupling (Cm), (see paragraphs [0038]-[0039]).
For claim 2, Figure 15 of Fujiyoshi teaches wherein the amplifier stage with continuously variable gain and bandwidth (11, Cfb, switches connected with Cfb, Cds) is a voltage controllable amplifier stage with continuously variable gain and bandwidth (11, Cfb, switches connected with Cfb, Cds), which is controllable by a loop control voltage (Dds) derived from at least one output (Vout) of the edge detection stage (Csp, Csn, 24).
For claim 3, Figure 15 of Fujiyoshi teaches a differential integrator stage (25) connected to the at least one output (Vout) of the edge detection stage (Csp, Csn, 24), the differential integrator stage (25) configured to derive the loop control voltage (Dds) from the at least one output (Vout) of the edge detection stage (Csp, Csn, 24).
For claim 18, Figure 1 of Fujiyoshi teaches wherein the electrode (sensor electrode 2) is configured to receive the input signal by the electrode capacitive coupling (Cm) to a capacitive area of an electronic display (touch pad), the electronic display being outside of the position indicator (1), (see par. [0038]-[0039]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiyoshi (US 2014/0035601, Figure 15) in view of Figure 10 of Fujiyoshi (US 2014/0035601) .
For claim 11, Figure 15 of Fujiyoshi teaches wherein the amplifier stage with continuously variable gain and bandwidth (11, Cfb, switches connected with Cfb, and Cds) comprises: an amplifier (11) with an amplifier input (“-” terminal in 11) coupled to the signal input via a series input capacitor (Cm, see Figure 1, note that Figure 15 is a detail of Electrostatic Capacitance Detection Circuit 1 in Figure 1) and an amplifier output (output of 11) connected to the edge detection stage (Csp, Csn, 24), the series input capacitor (Cm, see Figure 1, note that Figure 15 is a detail of Electrostatic Capacitance Detection Circuit 1 in Figure 1) connected between the signal input and the amplifier input (“-” terminal in 11), a first amplifier branch (the feedback of Cfb through both ϕ2) comprising a feedback capacitor (Cfb) parallel with the amplifier (11) (when ϕ1 is ON, or ϕ2 is ON). Figure 15 of Fujiyoshi does not teach the amplifier stage comprising a second amplifier branch comprising a feedback resistor that is parallel to at least one from among the first amplifier branch and the amplifier. However, Figure 10 of Fujiyoshi in the same reference teaches an amplifier stage comprising a second amplifier branch (12) comprising a feedback resistor (Rfb) that is parallel to at least one from among the first amplifier branch (Cfb, ϕ1, ϕ2) and the amplifier (11). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the circuit in Figure 15 of Fujiyoshi to include a second amplifier branch (12) comprising a feedback resistor (Rfb) that is parallel to at least one from among the first amplifier branch (Cfb, ϕ1, ϕ2) and the amplifier (11), as taught in Figure 10 of Fujiyoshi in the same reference, for the purpose of providing a specific time constant (Cfb.Rfb) and avoiding the great deterioration in the SN ratio of the output of the amplifier stage.
For claim 12, in the above modification/combination of Figure 15 of Fujiyoshi, it is obvious that the feedback resistor (Rfb) is controllable by a loop control voltage to control the resistance value so as to set the time-constant to a specific value.
For claim 13, in the above modification/combination of Figure 15 of Fujiyoshi, it is obvious the feedback resistor is controllable by the loop control voltage (Cds) derived from at least one output (Dout) of the edge detection stage (Csp, Csn, 24) so as to set the time-constant to a specific value and to control the gain of the amplifier stage.
For claim 15-16, in the above modification/combination of Figure 15 of Fujiyoshi, wherein the amplifier stage with continuously variable gain and bandwidth (11, Cfb, switches connected with Cfb and Cds in Figure 15 combines with Rfb in Figure 10) is a voltage controllable amplifier stage with continuously variable gain and bandwidth (11, Cfb, switches connected with Cfb and Cds in Figure 15 combines with Rfb in Figure 10), which is controllable by a loop control voltage (Dds) derived from at least one output of the edge detection stage (Csp, Csn, 24), wherein at least one from among the series input capacitor (Cds) or the feedback capacitor (Cfb) is implemented as a varactor or a voltage controlled capacitor (voltage control Cds and/or Cfb) and the loop control voltage (Dds) is configured to control the bias voltage across such varactor or voltage controlled capacitor (Cds); wherein the amplifier comprises a bias current control input (the bias at the “-” terminal of 11) wherein the loop control voltage (Dds) is configured to control an amount of bias current applied to the bias current control input (by controlling Cds to control the bias current to the “-” terminal of 11).
Allowable Subject Matter
Claims 4-10 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 02/27/26 have been fully considered but they are not persuasive.
Applicant argues that independent claim 1 is not anticipated by Fujiyoshi, at least for reciting "an amplifier stage with continuously variable gain and bandwidth, the amplifier stage coupled between the signal input and the edge detection stage and configured to amplify the input signal provided by the signal input." For example, nothing has been found in Fujiyoshi to disclose or suggest that the alleged amplifier stage ("11, Cfb, switches connected with Cfb, Cds") has "continuously variable gain and bandwidth" as claimed. The Office Action also does not explicitly articulate how Fujiyoshi is allegedly to describe an amplifier stage "with continuously variable gain and bandwidth" as claimed. The only explicit mention of "gain" in Fujiyoshi appears to be that "a gain of the output digital value can be adjusted by changing the size of the delta sigma feedback capacitor Cds." See Fujiyoshi at [0069] and [0101]. However, such description appears to suggest fixing a gain of an output digital value based on a certain size of the delta sigma feedback capacitor Cds, rather than having "an amplifier stage with continuously variable gain and bandwidth" as claimed.
However, the above argument is not persuasive because, for broadest reasonable interpretation, Figure 15 of Fujiyoshi teaches an amplifier stage (11, Cfb, switches connected with Cfb, and Cds) with continuously variable gain and bandwidth, the amplifier stage (11, Cfb, switches connected with Cfb, and Cds) coupled between the signal input (Ain) and the edge detection stage (Csp, Csn, 24) and operable to amplify the input signal (Ain) provided by the signal input (Ain). Note that the gain of the amplifier stage in Figure 15 of Fujiyoshi depends on Cds and as long as Cds varies then the gain and bandwidth of the amplifier stage also changes/varies. Thus, for broadest reasonable interpretation Figure 15 of Fujiyoshi teaches all the elements of claim 1 with the recited connections and operations as recited in the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
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/Long Nguyen/
Primary Examiner
Art Unit 2842