DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
Step 1:
All claims recite a method or a device which are eligible statutory categories.
Step 2A prong 1:
Claims 1 and 11 recite determining, based on the memory error data and a memory physical structure, a prediction area that is to be affected by the memory error in the future and a time range in which the error occurs in the prediction area. A determination is a mental process.
Claims 4 and 14 recite determining a memory error area based on the space information; determining the prediction area based on the memory error area and the memory physical structure; and determining, based on the memory error area and the time information which are still mental processes based on data received.
Claim 6 recites classifying the memory cell in which the error occurs based on a column address range of the memory cell in the memory and a row address range of the memory cell in the memory, classification is a mental process similar to determining.
Claims 8 and 18 recite wherein the prediction area comprises at least one of the following: when the memory error area is a single bit, the prediction area is a memory cell, these are only pre-determined rules for how the received data is interpreted.
Claims 9 and 19 recite determining a probability of an uncorrectable error which is still making a determination. Probability itself is a mathematical concept.
Step 2A prong 2:
This judicial exception is not integrated into a practical application by additional elements.
Claims 1 and 11 recite wherein the memory physical structure indicates a connection relationship between memory cells comprised in a memory which are generic computer hardware, “connection relationship” is still a high level of generality.
Claims 2 and 12 recite a temporal distribution feature of the memory error, and a spatial distribution feature of the location which are just types of information that have been obtained.
Claims 3 and 13 recite a main-word line, a sub-word line, a sub-word line driver, a column selection line, a bit line, a sense amplifier, a row address decoder, and a column address decoder, how the memory cells are connected are only a field of use for the method to apply to (MPEP 2106.04(d)(2)).
Claims 4 and 14 recite a prediction area that is to be affected by the memory error in the future and a time range in which the error occurs. The area is the same generic memory hardware and a time range is still just something determined by the mental process.
Claims 5 and 15 recite prompting a user, which is only extra-solution activity, data output.
Claims 6 and 16 recite wherein the space information comprises a column address and a row address of the memory cell in which the error occurs in the memory which are the intended use of the invention.
Claims 7 and 17 recite wherein the memory error area comprises at least one of the following: a dual inline memory module, a rank, a memory chip, a bank group, a bank, a subarray, a matrix, a row, a column, or a memory cell which are further clarification of the field of use.
Claim 8 and 18 recite when the memory error area is a single bit, the prediction area is a memory cell; when the memory error area is a single row, the prediction area is a main-word line control area…which are all specific error and area types, but still amount to merely a field of use.
Claims 9 and 19 recite at least two memory chips, wherein the memory area comprises one of the memory error area and the prediction area which are generic computer hardware.
Claims 10 and 20 recite obtaining the memory error data from memory logs which is mere data gathering.
Step 2 B:
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Claims 1 and 11, the obtaining memory error data, wherein the memory error data comprises time information of a memory error and space information of the memory error when the memory error occurs is extra-solution activity, mere data gathering. How the data is obtained is not specified, so making a determination with it can be practically performed in the human mind.
Claims 2 and 12 recite temporal and spatial features, but not calculating these distributions. It still only gathers information from the features, and does not amount to more than extra solution activity.
In claims 3 and 13, only details about the memory structure are described, no actions to create more than the field of use.
For claims 4 and 14, the predictions are merely the result of making the determination.
For claims 5 and 15, prompting a user is well understood, routine and conventional, MPEP 2106.05(d)II.
For claims 6 and 16, it only describes the information being obtained and making classifications.
For claims 7 and 17, they contain nothing in addition to describing the memory structure to amount to more than a field of use.
For claims 8 and 18, the error classification rules are sorting information received, which is well understood, routine and conventional.
For claims 9 and 19, determining a probability is like determining an estimated outcome, which is well understood routine and conventional, MPEP 2106.05(d)II.
For claims 10 and 20, receiving data logs is well understood routine and conventional.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-8, 10, 11, 13-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 20220350715) in view of Kim (US 20230076545).
Regarding claim 1, Zhou teaches A memory error prediction method, comprising: obtaining memory error data, wherein the memory error data comprises time information of a memory error (“In one example, dataset 210 includes a timestamp to indicate when errors occurred” ¶62”); and space information of the memory error when the memory error occurs (“the system can correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration. Thus, the system can account for rank, bank, row, column, or other information related to the physical organization and structure of the memory in predicting uncorrectable errors.” ¶26); and determining, based on the memory error data and a memory physical structure, a prediction area that is to be affected by the memory error in the future (“Thus, the system can account for rank, bank, row, column, or other information related to the physical organization and structure of the memory in predicting uncorrectable errors.” ¶26); wherein the memory physical structure indicates a connection relationship between memory cells comprised in a memory (“Data can be selected into the sense amplifiers to allow detection of the value stored in a bit cell or memory cell of the array. The dashed box that includes the intersection of the labeled row and column of the memory array.” ¶81).
Zhou does not teach and a time range in which the error occurs in the prediction area. Kim teaches and a time range in which the error occurs in the prediction area (“For example, the error profile precoder 1120 may precode the raw data and transmit it to a TTF and TBE calculation module 1122a (Time-To-Failure and Time Bet Error calculation module) so that the TTF and TBE calculation module 1122a may calculate a TTF value and a TBE value of the error occurring in the data” ¶49). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the fault analysis and location prediction methods of Zhou with the prediction of a time for errors as taught by Kim. This time data could be useful for the training of error prediction models (Kim ¶55).
Regarding claim 3, Zhou teaches wherein the memory physical structure comprises a connection relationship between memory cells to which a main-word line, a sub-word line, a sub-word line driver (“A runtime micro-level-fault-aware policy based on tracking error history can detect defective memory regions (e.g., worldline, bitline/DQ (data pin), subrange of wordline/bitline, row, column, device, rank) to infer whether a certain microlevel memory component (e.g., column, row) is faulty.” ¶27); a column selection line, a bit line, a sense amplifier (“The memory array includes rows (ROW) and columns (COL) of memory elements. Sense amplifier (SA) 344 represents a sense amplifier to stage data for a read from the memory array or for a write to the memory array.” ¶81 “Row decoder (DEC) 422 represents decoding hardware to select rows or wordlines for read, write, or other access” ¶85); and a column address decoder are connected (“Column decoder (DEC) 428 represents hardware to select the output columns or bitlines. Column decoder 428 selects bitlines based on column address information received for an operation.” ¶86).
Regarding claim 4, Zhou teaches wherein the determining, based on the memory error data and a memory physical structure, a prediction area that is to be affected by the memory error in the future and a time range in which the error occurs in the prediction area comprises: determining a memory error area based on the space information; determining the prediction area based on the memory error area and the memory physical structure; and determining, based on the memory error area and the time information, the time range in which the error occurs in the prediction area (“In one example, sparing 148 identifies a faulty region of memory associated with the faulty component or fault region prediction generated by UE analyzer 146.” ¶56).
Regarding claim 5, Kim teaches The method according to claim 4, wherein the method further comprises: prompting a user with the memory error area, the prediction area, and the time range (“At the same time, the memory controller 100 may notify the user of the memory system 10 that the predicted fault has an uncorrectable error.” ¶87).
Regarding claim 6, Zhou teaches The method according to claim 4, wherein the space information comprises a column address and a row address of the memory cell in which the error occurs in the memory (“In one example, the system tracks the subrange of the row containing the faulty cell or the faulty data unit in a defective memory region directory.” ¶98); and the determining a memory error area based on the space information comprises: classifying the memory cell in which the error occurs based on a column address range of the memory cell in the memory and a row address range of the memory cell in the memory, to obtain the memory error area (“The mapping of the spare row causes the physical address of the defective row to be associated with the spare row.” ¶50”).
Regarding claim 7, Zhou teaches The method according to claim 4, wherein the memory error area comprises at least one of the following: a dual inline memory module, a rank, a memory chip, a bank group, a bank, a subarray, a matrix, a row, a column, or a memory cell (“The analysis can apply to memory modules such as dual inline memory modules (DIMMs)” ¶28).
Regarding claim 8, Zhou teaches The method according to claim 7, wherein the prediction area comprises at least one of the following: when the memory error area is a single bit, the prediction area is a memory cell; when the memory error area is a single row, the prediction area is a main-word line control area; when the memory error area is a plurality of rows in a single matrix, the prediction area is a sub-word line driver control area; when the memory error area is a single column in a single matrix, the prediction area is a bit line control area; when the memory error area is a single column in a plurality of matrices, the prediction area is a sense amplifier control area; when the memory error area is a plurality of rows in a plurality of matrices, the prediction area is a row address decoder control area; or when the memory error area is a plurality of columns in a plurality of matrices, the prediction area is a column address decoder control area (“Based on the occurrence of multiple CEs in the same row, the system can make a computational determination that the row is faulty.” ¶83).
Regarding claim 10, Zhou teaches wherein the obtaining memory error data comprises: obtaining the memory error data from memory logs (“In one example, memory fault tracker 260 stores information from region directory 264 in cacheline sparing directory 270 (or simply, directory 270) or other information that stores log 268” ¶73).
Regarding claim 11, Zhou teaches A computing device, wherein the computing device comprises one or more memories and one or more processors, the one or more memories store a set of computer instructions (“System 100 illustrates memory coupled to a host. Host 110 represents a host computing platform, such as an SOC (system on a chip). Host 110 includes host processing elements (e.g., processor cores) represented by CPU (central processing unit) 112 to execute operations, and memory controller 116 to manage access to memory 130” ¶30); the set of computer instructions are executed by the one or more processors to: obtaining memory error data, wherein the memory error data comprises time information of a memory error (“In one example, dataset 210 includes a timestamp to indicate when errors occurred” ¶62”); and space information of the memory error when the memory error occurs (“the system can correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration. Thus, the system can account for rank, bank, row, column, or other information related to the physical organization and structure of the memory in predicting uncorrectable errors.” ¶26); and determining, based on the memory error data and a memory physical structure, a prediction area that is to be affected by the memory error in the future (“Thus, the system can account for rank, bank, row, column, or other information related to the physical organization and structure of the memory in predicting uncorrectable errors.” ¶26); wherein the memory physical structure indicates a connection relationship between memory cells comprised in a memory (“Data can be selected into the sense amplifiers to allow detection of the value stored in a bit cell or memory cell of the array. The dashed box that includes the intersection of the labeled row and column of the memory array.” ¶81).
Kim teaches and a time range in which the error occurs in the prediction area (“For example, the error profile precoder 1120 may precode the raw data and transmit it to a TTF and TBE calculation module 1122a (Time-To-Failure and Time Bet Error calculation module) so that the TTF and TBE calculation module 1122a may calculate a TTF value and a TBE value of the error occurring in the data” ¶49).
Regarding claims 13-18 and 20, Zhou and Kim teach the computing device of claim 11 and they recite the same additional limitations as claims 3-8 and 10 respectively.
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Kim in view of Jenkinson (US 20230222032).
Regarding claim 2, Zhou and Kim teach the method according to claim 1, but do not teach wherein the time information comprises a temporal distribution feature of the memory error, and the space information comprises a location of a memory cell in which the error occurs in the memory and a spatial distribution feature of the location.
Jenkinson teaches wherein the time information comprises a temporal distribution feature of the memory error, (“In some examples, such a counter may be associated with a threshold duration, such as monitoring or evaluating respective quantities of access errors within a time period (e.g., within a day or other static time interval, within a past 24 hours or other rolling time interval)” ¶32); and the space information comprises a location of a memory cell in which the error occurs in the memory and a spatial distribution feature of the location (“Thus, in accordance with examples as disclosed herein, one or more aspects of a system 100 may be configured to support an improved evaluation of errors associated with accessing a memory device 110 by evaluating a distribution (e.g., a spatial distribution, a physical distribution) of access errors associated with the memory device” ¶38). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the error analysis and prediction methods of Zhou and Lee with the spatial and temporal distribution of errors as taught by Jenkinson. This could improve an ability to attribute access errors to different components of the system (Jenkinson ¶38).
Regarding claim 12, Jenkinson teaches wherein the time information comprises a temporal distribution feature of the memory error, (“In some examples, such a counter may be associated with a threshold duration, such as monitoring or evaluating respective quantities of access errors within a time period (e.g., within a day or other static time interval, within a past 24 hours or other rolling time interval)” ¶32); and the space information comprises a location of a memory cell in which the error occurs in the memory and a spatial distribution feature of the location (“Thus, in accordance with examples as disclosed herein, one or more aspects of a system 100 may be configured to support an improved evaluation of errors associated with accessing a memory device 110 by evaluating a distribution (e.g., a spatial distribution, a physical distribution) of access errors associated with the memory device” ¶38).
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou, Kim and Kim (US 20220100395, which will be referred to as Kim+Lee for clarity).
Regarding claim 9, Zhou and Kim teach the method according to claim 1. They do not teach wherein the method further comprises: determining a probability of an uncorrectable error based on a probability of a correctable error in a same memory area in at least two memory chips, wherein the memory area comprises one of the memory error area and the prediction area.
Kim+Lee teach wherein the method further comprises: determining a probability of an uncorrectable error based on a probability of a correctable error in a same memory area in at least two memory chips, wherein the memory area comprises one of the memory error area and the prediction area (“In general, when a codeword error occurs, the memory system increases the codeword count value by one, and determines that the probability of an uncorrectable error (UE) is high when the counted codeword count value is greater than or equal to a reference value” ¶32). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the error analysis and prediction methods of Zhou and Kim with the determination of uncorrectable error probability as taught by Kim+Lee. Knowing that the probability of uncorrectable errors is high allows for preventative actions to be taken (Kim+Lee) ¶34.
Regarding claim 19, Kim+Lee teach wherein the method further comprises: determining a probability of an uncorrectable error based on a probability of a correctable error in a same memory area in at least two memory chips, wherein the memory area comprises one of the memory error area and the prediction area (“In general, when a codeword error occurs, the memory system increases the codeword count value by one, and determines that the probability of an uncorrectable error (UE) is high when the counted codeword count value is greater than or equal to a reference value” ¶32).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN KEVIN MCNAMARA whose telephone number is (703)756-1884. The examiner can normally be reached Monday-Friday 7:30-5:00 EST.
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/SEAN KEVIN MCNAMARA/Examiner, Art Unit 2113
/PHILIP GUYTON/Primary Examiner, Art Unit 2113