DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 – 4, 8, 10 – 14, and 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US Publication Number 2004/0186061, hereinafter “Oh”) in view of Karamcheti et al. (US Publication Number 2010/0374959, hereinafter “Karamcheti”).
4. As per claims 1, 11, and 18, Oh teaches a memory module, method, non-transitory computer-readable medium (figure 2C), comprising: configuring pins of a memory channel for synchronous communication (pin configuration for synchronous communication, paragraph 21); communicating, via at least a first pin of the pins configured for synchronous communication, between a volatile memory of a memory module and a memory controller (communication synchronous between volatile memory 104 and memory control 106, figure 2c); and communicating, via at least a second pin of the pins that is for asynchronous communication (pin handling translation for asynchronous communication along parallel port, paragraph 26), between a non-volatile memory (NVM 108, figure 2c) of the memory module and the memory controller (communication between control 106 and NVM 108, figure 2c, paragraph 26).
Oh does not appear to explicitly disclose a second pin of the pins that is repurposed for asynchronous communication, wherein the non-volatile memory transmits feedback to the memory controller via the second pin using an asynchronous protocol.
However, Karamcheti discloses a second pin of the pins that is repurposed for asynchronous communication, wherein the non-volatile memory transmits feedback to the memory controller via the second pin using an asynchronous protocol (DIMM sockets 115A…N in memory channels 113A/213A…N are wired to processor by PCB traces 125A…N and sockets, paragraph 26, module 214 routes traces through pads of edge connectors 301, figure 3, paragraphs 41 and 42, DRAM channel clocks data out on strobe lines, paragraph 30, where repurposing is seen in paragraph 28 where the meaning of some signal lines in the pre-existing interconnections may be changed to appropriately control the non-DRAM type modules where the data strobe line becomes a feedback control signal line from non-volatile module to the memory controller, paragraph 29 and coupled to the heterogenous memory controller paragraph 30 where it removes need for constant polling for completion, paragraphs 14, 29, and 38 allowing for non-clock aligned asynchronous communication).
Oh and Karamcheti are analogous art because they are from the same field of endeavor memory controller handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Oh and Karamcheti before him or her, to modify the pin mapping of Oh to include the structure of Karamcheti because it would allow for enhanced functionality.
One of ordinary skill would be motivated to make such modification in order to enhance memory configuration (paragraph 3). Therefore, it would have been obvious to combine Karamcheti with Oh to obtain the invention as specified in the instant claims.
5. Oh modified by the teachings of Karamcheti as seen in claim 1 above, as per claims 2, 12, and 19, Oh teaches a memory module, method, non-transitory computer-readable medium, further comprising providing, via at least the second pin or a third pin of the pins that is repurposed for asynchronous communication, feedback to the memory controller based on a request for data received from the memory controller (figure 2c, asynchronous parallel port handling for memory controller, paragraph 26).
6. Oh modified by the teachings of Karamcheti as seen in claim 1 above, as per claims 3, 13, and 20, Oh teaches a memory module, method, non-transitory computer-readable medium, wherein the feedback indicates that the data requested by the memory controller is located in a data buffer of the non-volatile memory or loaded into the volatile memory (boot code buffer 120, figure 2c, paragraphs 20 and 49).
7. Oh modified by the teachings of Karamcheti as seen in claim 1 above, as per claims 4 and 14, Oh teaches a memory module and method, wherein the memory module provides the data requested by the memory controller with deterministic timing based on a send command received from the memory controller (send command received from memory controller, paragraphs 46 – 48).
8. Oh modified by the teachings of Karamcheti as seen in claim 1 above, as per claim 8, Oh teaches a memory module, wherein the feedback includes a first time slot for the memory module and a second time slot for a second memory module (time slot, paragraph 42).
9. Oh modified by the teachings of Karamcheti as seen in claim 1 above, as per claim 10, Oh teaches a memory module, wherein the feedback includes row address select (RAS) (row address strobe signal, paragraph 31) information of the memory module.
Allowable Subject Matter
10. Claims 5 – 7, 9 and 15 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 – 20 have been considered but are moot because the new ground of rejection in view Karamcheti of does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following prior art references have teachings of volatile and non-volatile memory handling with a memory controller for synchronous and asynchronous communication: Lee/Abdulla.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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