DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 11, and 12 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 20 of U.S. Patent No. 12,189,546; claims 4 and 20 of U.S. Patent No. 11,397,698; claims 1 and 20 of U.S. Patent No. 10,621,119. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by the patented parent claims.
Instant Application
12,189,546
11,397,698
10,621,119
Claim 1 A memory module comprising: a memory channel comprising pins configured for synchronous communication; a volatile memory configured to communicate with a memory controller via at least a first pin of the pins configured for synchronous communication; and a non-volatile memory configured to communicate with the memory controller via at least a second pin of the pins that is repurposed for asynchronous communication.
Claim 2. The memory module of claim 1, wherein the memory module provides, via at least the second pin or a third pin of the pins that is repurposed for asynchronous communication, feedback to the memory controller based on a request for data received from the memory controller.
Claim 1
a non-volatile memory; and
an asynchronous memory interface to interface with a memory controller,
wherein the asynchronous memory interface uses a memory channel that is operable for synchronous data communication between the memory controller and the device to send a device feedback indicating a status of the device to the memory controller in response to a data access request received from the memory controller.
Claim 4
a non-volatile memory; and an asynchronous memory interface to interface with a memory controller, wherein the asynchronous memory interface uses one or more repurposed pins of a double data rate (DDR) memory channel that is operable for synchronous data communication between the memory controller and the memory module to asynchronously access data stored in the non-volatile memory and synchronously or asynchronously send the data to the memory controller using the one or more repurposed pins via the DDR memory channel;
wherein the memory module asynchronously sends a device feedback indicating a status of the memory module to the memory controller using the one or more repurposed pins of the DDR memory channel in response to a data access request received from the memory controller, and wherein the memory controller synchronously sends data requested by the data access request using the one or more pins of the DDR memory channel based on the status of the memory module
Claim 1
a volatile memory; a non-volatile memory; and an asynchronous memory interface to interface with a memory controller, wherein the asynchronous memory interface uses repurposed pins of a double data rate (DDR) memory channel in addition to pins of the DDR memory channel that are used for synchronous data access to the volatile memory to send an asynchronous data stored in the non-volatile memory to the memory controller, wherein the asynchronous data is device feedback indicating a status of the non-volatile memory, and the status of the non-volatile memory is asynchronously sent to the memory controller using one or more of the repurposed pins, and wherein the memory controller synchronously sends data over the pins of the DDR memory channel in response to the status that is received asynchronously.
Claim 11. A method comprising: configuring pins of a memory channel for synchronous communication; communicating, via at least a first pin of the pins configured for synchronous communication, between a volatile memory of a memory module and a memory controller; and communicating, via at least a second pin of the pins that is repurposed for asynchronous communication, between a non-volatile memory of the memory module and the memory controller.
12. The method of claim 11, further comprising providing, via at least the second pin or a third pin of the pins that is repurposed for asynchronous communication, feedback to the memory controller based on a request for data received from the memory controller.
Claim 20. A method comprising: providing an asynchronous memory interface between a memory controller and a device over a memory channel that is operable for synchronous data communication between the memory controller and the memory module, wherein device comprises a non-volatile memory; asynchronously sending a device feedback indicating a status of the device to the memory controller in response to a data access request received from the memory controller; and sending the data to the memory controller via the memory channel.
Claim 20. A method comprising: providing an asynchronous memory interface between a memory controller and a memory module over a double data rate (DDR) memory channel that is operable for synchronous data communication between the memory controller and the memory module, wherein the memory module comprises a non-volatile memory; asynchronously accessing data stored in the non-volatile memory of the memory module, from the memory controller; and synchronously or asynchronously sending the data to the memory controller using one or more repurposed pins via the DDR memory channel.
Claim 20. A method comprising: providing an asynchronous memory interface between a memory controller and a memory module, wherein the memory module comprising a volatile memory and a non- volatile memory; sending device feedback of the memory module to the memory controller using repurposed pins of a double data rate (DDR) memory channel in addition to pins of a DDR memory channel that are used for synchronous data access to the volatile memory of the memory module; temporally dividing the device feedback in a plurality of time slots; and assigning each of the time slots for each DIMM of multiple DIMMs, wherein each time slot of the device feedback includes a transaction ID indicating the corresponding DIMM.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 – 4, 8 – 14, and 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US Publication Number 2004/0186061, hereinafter “Oh”) in view of Gupta et al. (US Publication Number 2014/0160876, hereinafter “Gupta”).
5. As per claims 1, 11, and 18, Oh teaches a memory module, method, non-transitory computer-readable medium (figure 2C), comprising: configuring pins of a memory channel for synchronous communication (pin configuration for synchronous communication, paragraph 21); communicating, via at least a first pin of the pins configured for synchronous communication, between a volatile memory of a memory module and a memory controller (communication synchronous between volatile memory 104 and memory control 106, figure 2c); and communicating, via at least a second pin of the pins that is for asynchronous communication (pin handling translation for asynchronous communication along parallel port, paragraph 26), between a non-volatile memory (NVM 108, figure 2c) of the memory module and the memory controller (communication between control 106 and NVM 108, figure 2c, paragraph 26).
Oh does not appear to explicitly disclose a second pin of the pins that is repurposed.
However, Gupta discloses a second pin of the pins that is repurposed (paragraphs 45 – 47, repurpose pins for alternate configuration).
Oh and Gupta are analogous art because they are from the same field of endeavor memory controller handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Oh and Gupta before him or her, to modify the pin mapping of Oh to include the swizzling of Gupta because it would allow for enhanced functionality.
One of ordinary skill would be motivated to make such modification in order to enhance memory controller functionality and configuration therein (paragraph 5). Therefore, it would have been obvious to combine Gupta with Oh to obtain the invention as specified in the instant claims.
6. Oh modified by the teachings of Gupta as seen in claim 1 above, as per claims 2, 12, and 19, Oh teaches a memory module, method, non-transitory computer-readable medium, further comprising providing, via at least the second pin or a third pin of the pins that is repurposed for asynchronous communication, feedback to the memory controller based on a request for data received from the memory controller (figure 2c, asynchronous parallel port handling for memory controller, paragraph 26).
7. Oh modified by the teachings of Gupta as seen in claim 1 above, as per claims 3, 13, and 20, Oh teaches a memory module, method, non-transitory computer-readable medium, wherein the feedback indicates that the data requested by the memory controller is located in a data buffer of the non-volatile memory or loaded into the volatile memory (boot code buffer 120, figure 2c, paragraphs 20 and 49).
8. Oh modified by the teachings of Gupta as seen in claim 1 above, as per claims 4 and 14, Oh teaches a memory module and method, wherein the memory module provides the data requested by the memory controller with deterministic timing based on a send command received from the memory controller (send command received from memory controller, paragraphs 46 – 48).
9. Oh modified by the teachings of Gupta as seen in claim 1 above, as per claim 8, Gupta teaches a memory module, wherein the feedback includes a first time slot for the memory module and a second time slot for a second memory module (time slot, paragraph 40).
10. Oh modified by the teachings of Gupta as seen in claim 1 above, as per claim 9, Gupta teaches a memory module, wherein the first time slot (time slot, paragraph 40) is associated with a first transaction ID and the second time slot is associated with a second transaction ID different from the first transaction ID (transaction ID associated with translated physical address per request, paragraphs 38 and 39).
11. Oh modified by the teachings of Gupta as seen in claim 1 above, as per claim 10, Oh teaches a memory module, wherein the feedback includes row address select (RAS) (row address strobe signal, paragraph 31) information of the memory module.
Allowable Subject Matter
12. Claims 5 – 7 and 15 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following prior art references have teachings of volatile and non-volatile memory handling with a memory controller for synchronous and asynchronous communication: Bartoli/Best/Ellerbrok/Gillingham/McVay/Mills/Nellans/
Qawami/Shallal/Sinclair/Stolt/Vijayrao/Ware.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184