DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending in this application.
Election/Restrictions
Applicant's election with traverse of claims 1-7 and 11-15 in the reply filed on 07/20/2026 is acknowledged. The traversal is on the grounds that restriction is based on alternative embodiments and there is no serious search burden. This is not found persuasive because:
On pages 1-2 of Response to election filed 07/20/2026, applicant argues
The features by which the species differ, namely the particular implementations of the first and second circuits (a ring oscillator and an inverter in Species I, a regulator and a unity-gain buffer in Species II, and a level-shifter output stage and a buffer in Species III), appear to be alternative examples of how that common concept is embodied, rather than separate inventions. Because the species are alternative embodiments of a single inventive concept commonly claimed through generic claim 1, Applicant submits that they are not patentably distinct.
Examiner agrees that the species are alternative embodiments. Hence, a species restriction is appropriate.
On page 2 of Response to election filed 07/20/2026, applicant argues
Second, and independently, the requirement does not establish a serious search or examination burden.
Examiner disagrees respectfully.
The requirement is still deemed proper and is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 10/17/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11 and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Maruyama (US 20230146002 A1).
Regarding claim 1, Maruyama teaches a semiconductor device (i.e. semiconductor device 1, figs.2-3) comprising a semiconductor chip (i.e. primary side chip 10, secondary side chip 20, figs.2-3) including a first circuit region (i.e. primary side chip 10, figs.2-3), a second circuit region (i.e. secondary side chip 20, figs.2-3) with a ground voltage different from a ground voltage of the first circuit region (e.g. GND2 is different from GND1, figs.2-3), a first protection element ([0022], power supply circuit 100 is configured to include a protection circuit) (i.e. electrostatic protection circuit 136, protection circuit 200, fig.3), and a resistor circuit (i.e. feedback voltage generation circuit 132, fig.3),
wherein the first circuit region includes:
a first terminal (i.e. VDD1 terminal 5, figs.2-3) to which a power supply voltage is supplied ([0022], an external voltage (Vdd1 or Vdd2));
a first circuit (i.e. high-speed circuit block A10 of primary side chip 10, figs.2-3) electrically connected to the first terminal (e.g. A10 is connected to VDD1 via 100, figs.2-3); and
a second circuit (i.e. first level shifter 104, fig.2) electrically connected to the first terminal and the first circuit (e.g. 104 is connected to VDD1 and A10, figs.2-3) and having a smaller power consumption than the first circuit ([0024], the first level shifter 104 converts a 5-volt square wave that is a high input to a 1.5-volt square wave),
wherein the second circuit region includes a third circuit (i.e. high-speed circuit block A10 of secondary side chip 20, figs.2-3) electrically connected to the second circuit (e.g. A10 is connected to 104, fig.2), wherein the first circuit and the third circuit mutually input and output unidirectional or bidirectional signals via the second circuit ([0022], the power supply circuit 100 regulates an external voltage (Vdd1 or Vdd2) … supplies it to the high-speed circuit block A10),
wherein the first protection element is electrically connected to a first node (e.g. node between LDO 100 and level shifter 104, fig.2) which electrically connects the first terminal and the second circuit (e.g. first node connects VDD1 and 104, fig.2), and
wherein the resistor circuit is provided between the first node and a second node (e.g. node between 132 and 130, fig.3) which electrically connects the first terminal, the first circuit, and the second circuit (e.g. second node electrically connects VDD1, A10 on primary side chip and A10 on secondary side chip, figs.2-3) and is located upstream of the first node (e.g. second node is within LDO 100 and first node is on output side of LDO, fig.2).
Regarding claim 11, Maruyama teaches the semiconductor device according to claim 1, wherein the resistor circuit is formed of a resistor (e.g. resistors R12 and R14, fig.3).
Regarding claim 13, Maruyama teaches the semiconductor device according to claim 1, wherein the first protection element is formed of a PMOS transistor or an NMOS transistor ([0038], electrostatic protection transistor is, for example, an NMOS (n-Channel Metal-Oxide Semiconductor) transistor and is a so-called “ggNMOS (Grounded Gate NMOS) transistor”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Maruyama (US 20230146002 A1), and further in view of Davis (US 5200733 A).
Regarding claim 12, Maruyama (US 20230146002 A1) teaches the semiconductor device according to claim 1.
Maruyama does not teach, wherein the resistor circuit is formed of a transistor.
Davis teaches in a similar field of endeavor of resistor structure and method of fabrication, resistor circuit is formed of a transistor (e.g. base region 38 corresponds to resistive region 12, fig.9).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the resistor circuit is formed of a transistor in Maruyama, as taught by Davis, as it provides the advantage of reduced surface area for contacts and improves planarity.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Maruyama (US 20230146002 A1), and further in view of Altolaguirre (US 20140063663 A1).
Regarding claim 14, Maruyama teaches the semiconductor device according to claim 1.
Maruyama does not teach, wherein the first protection element is formed of a plurality of diodes.
Altolaguirre teaches in a similar field of endeavor of ESD clamp circuit, a first protection element is formed of a plurality of diodes (i.e. conducting string 210, fig.5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the first protection element is formed of a plurality of diodes in Maruyama, as taught by Altolaguirre, as it provides the advantage of having flexibility in design by including a number of diodes that are desired for a threshold voltage.
Allowable Subject Matter
Claims 2-7 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Maruyama (US 20230146002 A1) teaches the semiconductor device according to claim 1, further comprising:
a second terminal supplied with the ground voltage of the second circuit region (e.g. terminal at GND2, fig.2) and electrically connected to the third circuit (e.g. GND2 is connected to A10 on secondary side chip, fig.2).
Maruyama does not teach, a second protection element connected to electrically short-circuit the first terminal and the second terminal, wherein an impedance value of the resistor circuit is larger than that of the second protection element.
Prior art Narita (US 9647647 B2), Salcedo (US 8665571 B2) and Kitagawa (US 20050135033 A1) have been considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “a second protection element connected to electrically short-circuit the first terminal and the second terminal, wherein an impedance value of the resistor circuit is larger than that of the second protection element.”
Claims 3-7 and 15 are indicated as allowable, as they depend on allowable claim 2.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 08/31/2026
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