DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-9, 11, 19, 20-21, and 23-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MANUSHAROW et al. (US 20140264791 hereinafter Manusharow).
In regards to claim 1, Manusharow discloses;” A device comprising: a substrate (Fig. 1 (12)) having a first side and an opposing second side (Fig. 1 (shown)); a first die on the first side of the substrate; a second die on the first side of the substrate (Fig. 1 (14, 16)); a bridge in the substrate (Fig. 1 (28)), the bridge comprising a layer of mold material (abstract, paragraph 0016 where the substrate is capable of being formed from various materials including molding), and the bridge having a top side below the first side of the substrate (Fig. 1 (shows the top surface of the bridge is below the top surface of the substrate and under the chips); a first interconnect electrically coupling the first die to the substate (Fig. 1 (C4 32)); a second interconnect electrically coupling the second die to the substrate (Fig. 1 C4 (30)); a third interconnect electrically coupling the first die to the bridge; a fourth interconnect electrically coupling the second die to the bridge (Fig. 1 (shows chip (14) electrically connected to chip (16)); wherein the bridge includes: a first pad on the layer of mold material electrically coupled with the third interconnect, and a second pad on the layer of mold material electrically coupled with the fourth interconnect, the second pad electrically coupled with the first pad; and an interconnect on the second side of the substrate, the interconnect including solder (Fig. 1 (shown), paragraph 0017).”
In regards to claim 2, Manusharow discloses;” The device of claim 1, further comprising: a fifth interconnect electrically coupling the first die to the bridge; a sixth interconnect electrically coupling the second die to the bridge; a third pad on the layer of mold material coupled with the fifth interconnect; and a fourth pad on the layer of mold material coupled with the sixth interconnect, the third pad electrically coupled with the fourth pad (Fig. 1 (shows multiple chip to bridge interconnects)).”
In regards to claim 5, Manusharow discloses;” The device of claim 1, wherein the substrate includes a cavity and the bridge is in the cavity (Fig. 1 (shows the bridge is embedded in substrate, abstract, paragraph 0019).”
In regards to claim 6, Manusharow discloses;” The device of claim 1, wherein the layer of mold material comprises a first layer of mold material, and the bridge comprises a second layer of mold material, the first layer of mold material over the second layer of mold material Fig. 1 (shown)).”
In regards to claim 7, Manusharow discloses;” The device of claim 6, further comprising a via in the second layer of mold material, the via including copper (paragraph 0021).”
In regards to claim 8, Manusharow discloses;” The device of claim 6, wherein the first layer of mold material and the second layer of mold material comprise are the same mold material (paragraph 0016, where the layers are of a dielectric layer suggesting they are the same).”
In regards to claim 9, Manusharow discloses;” The device of claim 8, wherein the mold material comprises an epoxy (Paragraph 0016 where the bridge is capable of being made with epoxy).”
In regards to claim 11, Manusharow discloses;” The device of claim 1, further comprising an encapsulant material at least partially surrounding the layer of mold material (Fig. 1 (shows the bridge is embedded in substrate, abstract, paragraph 0019).”
In regards to claim 19, Manusharow discloses;” A device comprising: a substrate (Fig. 1 (12)) including a cavity (Fig. 1 (shows the bridge is embedded in substrate, abstract, paragraph 0019); a first die on the substrate; a second die on the substrate (Fig. 1 (14, 16)); a bridge in the cavity (Fig. 1 (28)) of the substrate, and the bridge having a top side below a top side of the substrate (Fig. 1 (shows the top surface of the bridge is below the top surface of the substrate and under the chips); a first interconnect electrically coupling the first die to the substate (Fig. 1 (C4 32)); a second interconnect electrically coupling the second die to the substrate (Fig. 1 C4 (30)); a third interconnect electrically coupling the first die to the bridge; and a fourth interconnect electrically coupling the second die to the bridge (Fig. 1 (shown)); wherein the bridge includes: a first layer comprising a mold material, (paragraph 0016, where the layers are of a dielectric layer suggesting they are the same) a second layer over the first layer (Fig. 1 (shown)), a first metal pad on the second layer coupled with the third interconnect, a second metal pad on the second layer coupled with the fourth interconnect, and a metal trace on the second layer coupled with the first pad and the second pad (Fig. 1 ).”
In regards to claim 20, Manusharow discloses;” The device of claim 19, wherein the second layer of the bridge comprises the mold material (paragraph 0016, where the layers are of a dielectric layer suggesting they are the same).”
In regards to claim 21, Manusharow discloses;” The device of claim 20, wherein the mold material comprises an epoxy (Paragraph 0016 where the bridge is capable of being made with epoxy).”
In regards to claim 23, Manusharow discloses;” The device of claim 19, wherein the bridge does not include a layer of solid silicon (paragraph 0003).”
In regards to claim 24, Manusharow discloses;” The device of claim 19, further comprising a via in the first layer of the bridge, the via including copper (paragraph 0021).”
In regards to claim 25, Manusharow discloses;” The device of claim 19, further comprising at least one electrical routing feature on the first layer of the bridge (Fig. 1 (shown)).”
In regards to claim 26, Manusharow discloses;” The device of claim 19, further comprising: fifth interconnect electrically coupling the first die to the bridge; a sixth interconnect electrically coupling the second die to the bridge; wherein the metal trace comprises a first metal trace, and the bridge further includes: a third metal pad on the second layer coupled with the fifth interconnect, a fourth metal pad on the second layer coupled with the sixth interconnect, and a second metal trace coupled with the third pad and the fourth pad (Fig. 1 (shown)).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-4, 10, 12-18, 23, and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over MANUSHAROW et al. (US 20140264791 hereinafter Manusharow) as applied to claims 1 8, 12-18, 22, and 27-28 above, and further in view of Gu et al. (US 9368450 hereinafter Gu).
In regards to claim 3, Manusharow discloses;” The device of claim 2, a first trace between the first pad and the second pad; and a second trace between the third pad and the fourth pad;”, but does not directly disclose;” wherein the first trace and the second trace are separated by a distance of approximately 10 micrometers or less.
However Gu discloses a similar structure (Fig. 3) of a bridge between two integrated circuits
(202 and 204) with interconnecting conductors shown in figure 5. Gu further discloses that the
conductors are 2 μm wide with a spacing of 2 μm (Col. 11, Lines 6-20). It would have been
obvious to one skilled in the art when forming high density conductor patterns to have them as
closes as possible. Therefore, using the dimensions for conductor spacing and widths of Gu with
the structure of Manusharow, the instant invention is disclosed.
In regards to claim 4, a modified Manusharow discloses;” The device of claim 3”, but does not directly disclose;” wherein the first trace has a first width of approximately 10 micrometers or less, and the second trace has a second width of approximately 10 micrometers or less.”
Gu discloses a similar structure (Fig. 3) of a bridge between two integrated circuits (202 and 204) with interconnecting conductors shown in figure 5. Gu further discloses that the conductors are 2 μm wide with a spacing of 2 μm (Col. 11, Lines 6-20). It would have been obvious to one skilled in the art when forming high density conductor patterns to have them as close as possible. Therefore, using the dimensions for conductor spacing and widths of Gu with the structure of Manusharow, the instant invention is disclosed.
In regards to claim 10, Manusharow discloses;” The device of claim 8, wherein the mold material includes a filler, the filler comprising one of silicon, aluminum, and carbon (Gu Col. 5, Lines 25-61).
In regards to claim 12, Manusharow discloses;” A device comprising: a substrate (Fig. 1 (12)) having a first side and an opposing second side (Fig. 1 (shown)); a first die on the first side of the substrate; a second die on the first side of the substrate (Fig. 1 (14, 16)); a bridge (Fig. 1 (28)) in the substrate and comprising a mold material (abstract, paragraph 0016 where the substrate is capable of being formed from various materials including molding), the bridge including a first routing layer (Fig. (shown)), and the bridge having a top side below the first side of the substrate (Fig. 1 (shows the top surface of the bridge is below the top surface of the substrate and under the chips); a first interconnect electrically coupling the first die to the substate (Fig. 1 (C4 32)); a second interconnect electrically coupling the second die to the substrate (Fig. 1 C4 (30)); a third interconnect electrically coupling the first die to the bridge; and a fourth interconnect electrically coupling the second die to the bridge (Fig. 1 (shows chip (14) electrically connected to chip (16));”, but does not directly disclose;” wherein the first routing layer includes: a first trace electrically coupling the third interconnect with the fourth interconnect, the first trace having a first width of approximately 10 micrometers or less, and a second trace having a second width of approximately 10 micrometers or less, wherein a distance between the first trace and the second trace is approximately 10 micrometers or less.”
However Gu discloses a similar structure (Fig. 3) of a bridge between two integrated circuits
(202 and 204) with interconnecting conductors shown in figure 5. Gu further discloses that the
conductors are 2 μm wide with a spacing of 2 μm (Col. 11, Lines 6-20). It would have been
obvious to one skilled in the art when forming high density conductor patterns to have them as
closes as possible. Therefore, using the dimensions for conductor spacing and widths of Gu with
the structure of Manusharow, the instant invention is disclosed.
In regards to claim 13, a modified Manusharow discloses;” The device of claim 12, further comprising a second routing layer, the first routing layer over the second routing layer (Fig. 1 (shown)).”
In regards to claim 14, a modified Manusharow discloses;” The device of claim 13, wherein the second routing layer includes a third trace having a third width of approximately 10 micrometers or less (Gu (Col, 11, Lines 6-20) conductors are 2 μm wide with a spacing of 2 μm).
In regards to claim 15, a modified Manusharow discloses;” The device of claim 12, further
comprising a via in the bridge, the via including copper (Manusharow paragraph 0021).
In regards to claim 16, a modified Manusharow discloses;” The device of claim 12, wherein the substrate includes a cavity and the bridge is in the cavity (Manusharow Fig. 1 (shows the bridge is embedded in substrate, abstract, paragraph 0019).”
In regards to claim 17, a modified Manusharow discloses;” The device of claim 12, further comprising an interconnect on the second side of the substrate, the interconnect including solder (Manusharow Fig. 1 (shown), paragraph 0017).”
In regards to claim 18, a modified Manusharow discloses;” The device of claim 12, further comprising an encapsulant at least partially surrounding the mold material (Manusharow Fig. 1 (shows embedded bridge enclosed in dialectic layer).
In regards to claim 22, Manusharow discloses;” The device of claim 20, wherein the mold material includes a filler, the filler comprising one of silicon, aluminum, and carbon (Gu Col. 5, Lines 25-61).
In regards to claim 27, Manusharow discloses;” The device of claim 26, wherein the
first metal trace and the second metal trace are separated by a distance of approximately 10
micrometers or less(Gu (Col, 11, Lines 6-20) conductors are 2 μm wide with a spacing of 2 μm).”
In regards to claim 28, Manusharow discloses;” The device of claim 27, wherein the
first metal trace has a first width of approximately 10 micrometers or less, and the second
metal trace has a second width of approximately 10 micrometers or less (Gu (Col, 11, Lines 6-
20) conductors are 2 μm wide with a spacing of 2 μm).”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL F MCALLISTER whose telephone number is (571)272-2453. The examiner can normally be reached Monday-Friday 7 AM-4 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL F MCALLISTER/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
