Prosecution Insights
Last updated: July 17, 2026
Application No. 18/918,478

ELECTRICAL INTERCONNECT BRIDGE

Non-Final OA §102§103
Filed
Oct 17, 2024
Priority
Apr 02, 2016 — continuation of 15/089,509 +2 more
Examiner
MCALLISTER, MICHAEL F
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
527 granted / 614 resolved
+25.8% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
14 currently pending
Career history
618
Total Applications
across all art units

Statute-Specific Performance

§103
68.0%
+28.0% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 614 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) s 1-2, 5-8, 11, 19-20, 24-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chin-Kwan Kim et al. (US 9642259 hereinafter Chin-Kwan). In regards to claim 1, Chin-Kwan discloses;” A device (abstract) comprising: a substrate (Fig. 4 (406)) having a first side and an opposing second side (Fig. 4 (shown)); a first die (Fig. 4 (400)) on the first side of the substrate; a second die (Fig. 4 (402)) on the first side of the substrate; a bridge in the substrate (Fig. 4 (404)), the bridge comprising a layer of mold material (abstract, where the bridge is capable of being multilayer independent dielectric insulating structures thus of a moldable material); a first interconnect electrically coupling the first die to the substate (Fig. 4 (420, 416)); a second interconnect electrically coupling the second die to the substrate (Fig. 4 (422,418); a third interconnect electrically coupling the first die to the bridge; a fourth interconnect electrically coupling the second die to the bridge (Fig. 5C shows multiple connection for the bridge); wherein the bridge includes: a first pad on the layer of mold material electrically coupled with the third interconnect, And a second pad on the layer of mold material electrically coupled with the fourth interconnect (Fig’s 4, 5A-C), the second pad electrically coupled with the first pad; and an interconnect on the second side of the substrate, the interconnect including solder (Fig. 4 shows the chips 400 and 402 connected to bridge by solder balls, Col. Lines 24-39).” In regards to claim 2, Chin-Kwan discloses;” The device of claim 1, further comprising: a fifth interconnect electrically coupling the first die to the bridge; a sixth interconnect electrically coupling the second die to the bridge; a third pad on the layer of mold material coupled with the fifth interconnect; and a fourth pad on the layer of mold material coupled with the sixth interconnect, the third pad electrically coupled with the fourth pad (Fig. 7A-C, Col. 7, Lines 1-36 disclose additional connections a possible).: In regards to claim 5, Chin-Kwan discloses;” The device of claim 1, wherein the substrate includes a cavity and the bridge is in the cavity (Fig. 4 shows (404) independent of (406) embedded in (406) cavity).” In regards to claim 6, Chin-Kwan discloses;” The device of claim 1, wherein the layer of mold material (Fig. 7A (624)) comprises a first layer of mold material, and the bridge comprises a second layer of mold material (Fig. 7A (628)), the first layer of mold material over the second layer of mold material (Fig. 7A shown)).” In regards to claim 7, Chin-Kwan discloses;” The device of claim 6, further comprising a via in the second layer of mold material, the via including copper (Col. 5, Lines 40-48).” In regards to claim 8, Chin-Kwan discloses;” The device of claim 6, wherein the first layer of mold material and the second layer of mold material comprise are the same mold material (Col. 2 Lines 56-65, where the layers are of a dielectric layer suggesting they are the same).” In regards to claim 11, Chin-Kwan discloses;” The device of claim 1, further comprising an encapsulant material at least partially surrounding the layer of mold material (Fig. 6 (614)).” In regards to claim 19, Chin-Kwan discloses;” A device (abstract) comprising: a substrate (Fig. 4 (406)) including a cavity (Fig. 4 shows (414) independent of (406) embedded in (406) cavity); a first die (Fig. 4 (400)) on the substrate; a second die (Fig. 4 (402)) on the substrate; a bridge (Fig. 6 (604)) in the cavity of the substrate; a first interconnect electrically coupling the first die to the substate; a second interconnect electrically coupling the second die to the substrate; a third interconnect electrically coupling the first die to the bridge; and a fourth interconnect electrically coupling the second die to the bridge; wherein the bridge includes: a first layer comprising a mold material (abstract, where the bridge is capable of being multilayer independent dielectric insulating structures thus of a moldable material), a second layer over the first layer, a first metal pad on the second layer coupled with the third interconnect, a second metal pad on the second layer coupled with the fourth interconnect, and a metal trace on the second layer coupled with the first pad and the second pad (Fig’s 6 and 7A-C shows disclosure).” In regards to claim 20, Chin-Kwan discloses;” The device of claim 19, wherein the second layer of the bridge comprises the mold material (Col. 2 Lines 56-65, where the layers are of a dielectric layer suggesting they are the same).” In regards to claim 24, Chin-Kwan discloses;” The device of claim 19, further comprising a via in the first layer of the bridge, the via including copper (Col. 5, Lines 40-48).” In regards to claim 25, Chin-Kwan discloses;” The device of claim 19, further comprising at least one electrical routing feature on the first layer of the bridge (Fig. 4 (412)).” In regards to claim 26, Chin-Kwan discloses;” The device of claim 19, further comprising: fifth interconnect electrically coupling the first die to the bridge; a sixth interconnect electrically coupling the second die to the bridge; wherein the metal trace comprises a first metal trace, and the bridge further includes: a third metal pad on the second layer coupled with the fifth interconnect, a fourth metal pad on the second layer coupled with the sixth interconnect, and a second metal trace coupled with the third pad and the fourth pad Fig. 5 (shown)). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3-4, 12-18, and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chin-Kwan Kim et al. (US 9642259 hereinafter Chin-Kwan as applied to claim 1 above, and further in view of Gu et al. (US 9368450 hereinafter Gu). In regards to claim 3, Chin-Kwan discloses;” The device of claim 2, further comprising: a first trace between the first pad and the second pad; and a second trace between the third pad and the fourth pad (Fig. 4 (shown));”, but does not directly disclose;” wherein the first trace and the second trace are separated by a distance of approximately 10 micrometers or less.” However Gu discloses a similar structure (Fig. 3) of a bridge between two integrated circuits (202 and 204) with interconnecting conductors shown in figure 5. Gu further discloses that the conductors are 2 μm wide with a spacing of 2 μm (Col. 11, Lines 6-20). It would have been obvious to one skilled in the art when forming high density conductor patterns to have them as closes as possible. Therefore, using the dimensions for conductor spacing and widths of Gu with the structure of Chin-Kwan, the instant invention is disclosed. In regards to claim 4, a modified Chin-Kwan discloses;” The device of claim 3, wherein the first trace has a first width of approximately 10 micrometers or less, and the second trace has a second width of approximately 10 micrometers or less.” Gu discloses a similar structure (Fig. 3) of a bridge between two integrated circuits (202 and 204) with interconnecting conductors shown in figure 5. Gu further discloses that the conductors are 2 μm wide with a spacing of 2 μm (Col. 11, Lines 6-20). It would have been obvious to one skilled in the art when forming high density conductor patterns to have them as closes as possible. Therefore, using the dimensions for conductor spacing and widths of Gu with the structure of Chin-Kwan, the instant invention is disclosed. In regards to claim 12, Chin-Kwan discloses;” A device (abstract) comprising: a substrate (Fig. 4 (406)) having a first side and an opposing second side; a first die on the first side of the substrate; a second die on the first side of the substrate (Fig. 4 (shown)); a bridge (Fig. 4 (404)) in the substrate and comprising a mold material (abstract, where the bridge is capable of being multilayer independent dielectric insulating structures thus of a moldable material), the bridge including a first routing layer (Fig. 7A ( 612)); a first interconnect electrically coupling the first die to the substate (Fig’s 6. 7A (shown)); a second interconnect electrically coupling the second die to the substrate (Fig. 6 (shown)); a third interconnect electrically coupling the first die to the bridge (Fig. 6 (616, 620)); and a fourth interconnect electrically coupling the second die to the bridge (Fig, 6 (618, 622)); wherein the first routing layer includes: a first trace (Fig. 6 (612)) electrically coupling the third interconnect with the fourth interconnect”, but does not directly disclose;” the first trace having a first width of approximately 10 micrometers or less, and a second trace having a second width of approximately 10 micrometers or less, wherein a distance between the first trace and the second trace is approximately 10 micrometers or less.” However Gu discloses a similar structure (Fig. 3) of a bridge between two integrated circuits (202 and 204) with interconnecting conductors shown in figure 5. Gu further discloses that the conductors are 2 μm wide with a spacing of 2 μm (Col. 11, Lines 6-20). It would have been obvious to one skilled in the art when forming high density conductor patterns to have them as closes as possible. Therefore, using the dimensions for conductor spacing and widths of Gu with the structure of Chin-Kwan, the instant invention is disclosed. In regards to claim 13, a modified Chin-Kwan discloses;” The device of claim 12, further comprising a second routing layer, the first routing layer over the second routing layer (Chin-Kwan Fig. 7A-C, where on conductor is on the layer above the other).” In regards to claim 14, a modified Chin-Kwan discloses;” The device of claim 13, wherein the second routing layer includes a third trace having a third width of approximately 10 micrometers or less (Gu (Col, 11, Lines 6-20) conductors are 2 μm wide with a spacing of 2 μm). In regards to claim 15, a modified Chin-Kwan discloses;” The device of claim 12, further comprising a via in the bridge, the via including copper (Chin-Kwan Col. 5, Lines 40-48). In regards to claim 16, a modified Chin-Kwan discloses;” The device of claim 12, wherein the substrate includes a cavity and the bridge is in the cavity (Chin-Kwan Fig. 4 shows (404) independent of (406) embedded in (406) cavity). In regards to claim 17, a modified Chin-Kwan discloses;” The device of claim 12, further comprising an interconnect on the second side of the substrate, the interconnect including solder (Chin-Kwan Fig. 4 shows the chips 400 and 402 connected to bridge by solder balls, Col. Lines 24-39). In regards to claim 18, a modified Chin-Kwan discloses;” The device of claim 12, further comprising an encapsulant at least partially surrounding the mold material (Chin-Kwan Fig. 6 (614)). In regards to claim 27, a modified Chin-Kwan discloses;” The device of claim 26, wherein the first metal trace and the second metal trace are separated by a distance of approximately 10 micrometers or less(Gu (Col, 11, Lines 6-20) conductors are 2 μm wide with a spacing of 2 μm). In regards to claim 28, a modified Chin-Kwan discloses;” The device of claim 27, wherein the first metal trace has a first width of approximately 10 micrometers or less, and the second metal trace has a second width of approximately 10 micrometers or less (Gu (Col, 11, Lines 6-20) conductors are 2 μm wide with a spacing of 2 μm). Allowable Subject Matter Claims 9-10, and 21-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL F MCALLISTER whose telephone number is (571)272-2453. The examiner can normally be reached Monday-Friday 7 AM-4 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL F MCALLISTER/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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Prosecution Timeline

Oct 17, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+6.2%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 614 resolved cases by this examiner. Grant probability derived from career allowance rate.

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