Prosecution Insights
Last updated: April 19, 2026
Application No. 18/918,496

DISPLAY APPARATUS AND ELECTRONIC DEVICE

Non-Final OA §103
Filed
Oct 17, 2024
Examiner
NGUYEN, KEVIN M
Art Unit
2628
Tech Center
2600 — Communications
Assignee
Sony Group Corporation
OA Round
3 (Non-Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
83%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
760 granted / 966 resolved
+16.7% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
23 currently pending
Career history
989
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
44.8%
+4.8% vs TC avg
§102
29.5%
-10.5% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 966 resolved cases

Office Action

§103
DETAILED ACTION Priority Attached is an attempt by the Office to electronically retrieve, under the priority document exchange program, the foreign application 2016-085682 to which priority is claimed has FAILED on 10/31/2024. Response to Arguments Applicant’s arguments filed 4/2/2026, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the prior art below. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2016/0322450 in view of Koo et al. US 2004/0169182. As to claim 1, Lee teaches a light emitting device (OLED device) and a light emitting element (OLED) (See ¶11-¶12 and Figure 5), a first transistor (a first transistor T6); a second transistor (a second transistor T1) above a silicon substrate (substrate 110) in a cross-sectional view (See ¶55-¶57); the capacitive element (a capacitor 137a, see at least ¶108) is located between the silicon substrate (silicon substrate 110, ¶117) and a gate of the first transistor (the gate 155f of the first transistor T6. See at least ¶100 and ¶104). Lee fails to teach "the first transistor and the second transistor are different in carrier mobility." Koo teaches a light emitting device (an organic EL display device 100, see ¶27, and Fig 1); a light emitting element (an organic EL element 160, see ¶27); a first transistor (a drive transistor 145, ¶28); a second transistor (a switching transistor 140, ¶28); a capacitive element (a capacitor 150, ¶28); the first transistor and the second transistor are different in carrier mobility (Koo's Par. 36-37 explained the driving transistor and the switching transistor have different mobilities). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the first transistor and the second transistor have different mobilities, as Koo teaches, to modify the first and second transistors of Lee. The motivation for doing so would improve reliability by controlling an amount of current flowing to an EL device while providing a high frequency transistor having a high mobility required in circuit mounting and a transistor having a low mobility for reducing an amount of current flowing to the EL device. See Koo ¶56-¶57. As to claim 2, Lee teaches the light emitting device according to claim 1, wherein the first transistor is configured to control the light emitting element (See Lee ¶63-¶64). As to claim 14, Lee teaches a display apparatus comprising a plurality of light emitting devices according to claim 1. (See Lee Abstract). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Koo as applied to claim 1 above, in view of Miyairi et al. US 2015/0187814. As to claim 10, Lee and Koo fail to teach the first transistor and the second transistor are formed at positions at least partially overlapping in a horizontal direction. Par. 275 and Fig. 7B of Miyairi explained the transistor 100 and the transistor 200 are formed at positions at least partially overlapping in a horizontal direction. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to have the transistor 100 and the transistor 200 are formed at positions at least partially overlapping in a horizontal direction, as Miyairi teaches, to modify the display device of Lee and Koo. The motivation for doing so would have been to reduce the area occupied by the elements. Miyairi ¶275. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 5-7, 10, 14, 20 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki US 2014/0008647 in view of Koo et al. US 2004/0169182. As to claim 1, Yamazaki teaches a light emitting device (the EL device, has a light-emitting element. See at least ¶230-¶232); a light emitting element (a light emitting element, see at least ¶232); a first transistor (a first transistor 610); a second transistor (a second transistor 740) above a silicon substrate (a silicon substrate 700, see ¶132-¶134) in a cross-sectional view (Figure 5A); the capacitive element (a capacitor 445a, see ¶145) is located between the silicon substrate (700) and a gate of the first transistor (the gate 401 of the first transistor 610. See at least ¶137, ¶145 and Figure 5A). Yamazaki fails to teach "the first transistor and the second transistor are different in carrier mobility." Koo teaches a light emitting device (an organic EL display device 100, see ¶27, and Fig 1); a light emitting element (an organic EL element 160, see ¶27); a first transistor (a drive transistor 145, ¶28); a second transistor (a switching transistor 140, ¶28); a capacitive element (a capacitor 150, ¶28); the first transistor and the second transistor are different in carrier mobility (Koo's Par. 36-37 explained the driving transistor and the switching transistor have different mobilities). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the first transistor and the second transistor have different mobilities, as Koo teaches, to modify the first and second transistors of Yamazaki. The motivation for doing so would improve reliability by controlling an amount of current flowing to an EL device while providing a high frequency transistor having a high mobility required in circuit mounting and a transistor having a low mobility for reducing an amount of current flowing to the EL device. See Koo ¶56-¶57. As to claim 2, Koo modified teaches the light emitting device according to claim 1, wherein the first transistor is configured to control the light emitting element (Par. 30 explained the driving transistor 145, a proper amount of current can flow through the EL device 160 per unit pixel, and a luminance appropriate for small scale high resolution can be generated while the switching characteristics of the switching transistor 140 are maintained. ). As to claim 5, Koo modified teaches the light emitting device according to claim 1, wherein the second transistor configured to control writing of an imaging signal. (See Koo ¶28). As to claim 6, Koo modified teaches the light emitting device according to claim 1, wherein a first carrier mobility of the first transistor is lower than a second carrier mobility of the second transistor. (Par. 30 explained a higher mobility as the switching transistor 140 and a transistor with a lower mobility as the driving transistor 145). As to claim 7, Koo modified teaches the light emitting device according to claim 1, wherein the first transistor is a thin film transistor. (Par. 27 explained thin film transistor is called a driving transistor 145). As to claim 10, Yamazaki teaches the first transistor and the second transistor are formed at positions at least partially overlapping in a horizontal direction. (Fig. 5A of Yamazaki shows the first transistor 610 and the second transistor 740 are formed at positions at least partially overlapping in a horizontal direction ). As to claim 14, Koo modified teaches a display apparatus comprising a plurality of light emitting devices according to claim 1. (See Koo Abstract). As to claim 20, Yamazaki teaches the light emitting device according to claim 1, wherein a gate of the second transistor is on the silicon substrate (the gate 401 of transistor 610 on the silicon substrate 700, see Yamazaki Figure 5A). As to claim 22, Yamazaki teaches light emitting device according to claim 2, wherein the capacitive element is located between the first transistor and the second transistor in the cross-sectional view. ( The capacitor 693 was located between the first transistor 740 and the second transistor 610. See Figure 5A ). As to claim 23, Yamazaki teaches light emitting device according to claim 12, wherein the capacitive element is on a same layer as a gate of the second transistor. (The capacitor 693 was on the same layer as the gate 410 of the second transistor 610. See Yamazaki Figure 5A and ¶145). Claim(s) 3-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki and Koo as applied to claim 1 above, in view of Minami et al. US 2012/0327058. As to claim 3, Yamazaki and Koo fail to teach one drain region of the first transistor is connected to a current supply line, another source region of the first transistor is connected to the light emitting element and a first electrode of the capacitive element, and a gate electrode of the first transistor is connected to a second electrode of the capacitive element. Minami teaches a display device 1Z having a drain D of the drive transistor 121 connected to a current supply line Vcc_H, a source S of the drive transistor 121 connected to the organic EL element 127 and a node ND122 of the capacitor 120, and a gate G of the drive transistor 121 connected to a node ND121 of the capacitor 120. See ¶122-¶123 and Fig 4. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to substitute an organic EL display device 100 taught by Yamazaki and Koo for the display device 1Z taught by Minami such that a drain D of the drive transistor 121 connected to a current supply line Vcc_H, a source S of the drive transistor 121 connected to the organic EL element 127 and a node ND122 of the capacitor 120, and a gate G of the drive transistor 121 connected to a node ND121 of the capacitor 120. The motivation for doing so would have been to suppress the luminance change due to the resistance component between the reference electric potential point and the display element by controlling the characteristics of the drive transistor. See Minami ¶12 . See KSR Int'l. Co. v. Teleflex, Inc., 550 U.S. 398, 401 (2007) (holding that the simple substitution of one known element for another to obtain predictable results is generally obvious). As to claim 4, Minami modified illustrates in figure 4 and par. 141-142 explained one drain D of the second transistor 125 is connected to a data line 106HS, another source S of the second transistor 125 is connected to the gate electrode G of the first transistor 121 and the second node ND121 of the capacitor 121, and a gate electrode G of the second transistor 125 is connected to a scanning line 104WS. As to claim 8, Minami modified teaches the light emitting device according to claim 1, wherein the first transistor is an n-channel type MOS transistor. (See Minami ¶93). Claim(s) 11, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki and Koo as applied to claim 1 above, in view of Yamashita et al. US 2013/0050067 hereinafter Yamashita ‘067. As to claim 11, Yamazaki and Koo fail to teach in the capacitive element, a source/drain region of the first transistor is used as a first electrode, and a source/drain region of the second transistor is used as a second electrode. Yamashita ‘067 modified teaches in the capacitive element, a source/drain region of the first transistor is used as a first electrode, and a source/drain region of the second transistor is used as a second electrode. (See Yamashita ‘067 abstract). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement in the capacitive element, a source/drain region of the first transistor is used as a first electrode, and a source/drain region of the second transistor is used as a second electrode, as Yamashita ‘067 teaches to modify Yamazaki and Koo. The motivation for doing so would have been to suppress the occurrence of the back gate effect (also referred to as a substrate bias effect), to attain stable operation of the driving circuit, and to suppress an increase in power consumption of the display device or the electronic apparatus. See Yamashita ‘067 ¶11. As to claim 17, Yamashita ‘067 modified teaches the display apparatus according to claim 15, wherein a first semiconductor layer of the first transistor is located between a top surface of the substrate and an anode electrode of the light emitting element in a cross-sectional view. (Yamashita ‘067 Par. 7 explained an n-channel drive transistor TDrv ( the n-channel interpreted a first semiconductor layer) located between the silicon substrate 10 and an anode 51 of the light-emitting unit ELP as shown in Figure 1). As to claim 19, Yamashita ‘067 modified teaches an electronic device comprising the display apparatus according to claim 14. (See Yamashita ‘067 ¶ 1, ¶8, and ¶11-¶12). Claims 12-13 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki ‘067 and Koo as applied to claim 1 above, in view of Yamashita et al. US 2015/0349005 hereinafter Yamashita ‘005. As to claims 12 and 21, Yamazaki ‘067 and Koo fail to teach the capacitive element is a Metal Insulator Semiconductor (MIS) capacitor. As to claim 13, Yamazaki ‘067 and Koo fail to teach a gate oxidized film thickness of the second transistor and an insulator film thickness of the MIS capacitor are different. Yamashita ‘005 teaches a metal-insulator-metal (MIS) capacitor 117. See Yamashita ‘005 ¶26 and Fig 10. Yamashita ‘005 in Par. 45, 55, and Fig 10 explained the MIS capacitor 117 and the gate oxide of transistor 115 has thickness different. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the MIS capacitor 117 and the gate oxide of transistor 115 has thickness different, as Yamashita ‘005 teaches, to modify Yamazaki ‘067 and Koo. The motivation for doing so would have been to reduce the thickness of the display device, and reduce power consumption. See Yamashita ‘005 ¶23. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki, Koo and Yamashita ‘067 as applied to claim 1 above, in view of Miyairi US 2015/0187814. As to claim 18, Yamazaki, Koo and Yamashita ‘067 fail to teach the display apparatus according to claim 17, wherein the first semiconductor layer is an oxide film. Miyairi teaches an organic electroluminescence (EL) element having the transistor 3300 is a transistor in which a channel is formed in a semiconductor including an oxide semiconductor. See Miyairi ¶232 and ¶366. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to substitute the first semiconductor taught by Yamazaki, Koo and Yamashita ‘067 for the oxide semiconductor taught by Miyairi. The motivation for doing so would have been to improve refresh operation is unnecessary or the frequency of refresh operation is extremely low. See Miyairi ¶366 . See KSR Int'l. Co. v. Teleflex, Inc., 550 U.S. 398, 401 (2007) (holding that the simple substitution of one known element for another to obtain predictable results is generally obvious). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Nguyen whose telephone is (571)272-7697. The examiner can normally be reached M-T 8am-5pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Kevin M Nguyen/Primary Examiner, Art Unit 2628 Telephone: (571) 272-7697 Email: kevin.nguyen2@uspto.gov
Read full office action

Prosecution Timeline

Oct 17, 2024
Application Filed
Oct 02, 2025
Non-Final Rejection — §103
Dec 23, 2025
Response Filed
Jan 29, 2026
Final Rejection — §103
Apr 01, 2026
Applicant Interview (Telephonic)
Apr 01, 2026
Examiner Interview Summary
Apr 02, 2026
Response after Non-Final Action
Apr 03, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
83%
With Interview (+4.6%)
2y 10m
Median Time to Grant
High
PTA Risk
Based on 966 resolved cases by this examiner. Grant probability derived from career allow rate.

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