DETAILED ACTION
Priority
Attached is an attempt by the Office to electronically retrieve, under the priority document exchange program, the foreign application 2016-085682 to which priority is claimed has FAILED on 10/31/2024.
Response to Amendment
This Office action is in response to the amendments filed on 06/25/2026. Claim 1 has been amended. Claims 2-23 have been canceled. Claims 24-42 have been added. Therefore, claims 1 and 24-42 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 24-42 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 33 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Amended claim 33 has been added new limitation “the second electrode of the first capacitive element is a portion of the silicon substrate” with no support in the original specification, as being new subject matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 26-27, 35-38 and 40-42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 2016/0005803) in view of Jintyou et al. (US 2015/0372023)
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As to claim 1, Ryu teaches a light emitting device (OLED device) and a light emitting element (OLED) (See Abstract and Figures 2-3), a first transistor (a first transistor DTr, see ¶57);a second transistor (a second transistor STr, see ¶57) above a silicon substrate (substrate 101, ¶58) in a cross-sectional view (in cross section. See ¶ 40); a first capacitive element (a capacitor Stgc, see at least ¶59-¶62) including a first electrode (106) and a second electrode (103) below the first electrode (106) in a cross-sectional view (a second storage electrode 106 overlaps the first storage electrode 103 in the cross-section, see ¶66, and Fig 3); the first electrode of the first capacitive element is located between the silicon substrate and a gate electrode of the first transistor ( the first storage electrode 103 is located between the substrate 101 and the gate electrode 120b of the first transistor DTr. See at least ¶75 and Fig 3).
Ryu fails to teach a silicon substrate.
Jintyou teaches a silicon substrate. See Jintyou ¶81.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the silicon substrate, as Jintyou teaches, to modify the first and second transistors of Ryu. The motivation for doing so would achieves lower power consumption of the circuit. See Jintyou ¶81.
As to claim 26, Ryu teaches light emitting device according to claim 1, wherein the first transistor is a thin film transistor. (See ¶117).
As to claim 27, Ryu teaches a first semiconductor layer (115, ¶70) of the first transistor is located between a top surface of the silicon substrate (101) and an anode electrode (165, ¶94, Fig 3) of the light emitting element (E, ¶93, Fig 3) in the cross-sectional view.
As to claim 35, Ryu teaches Figure 2 shows a first terminal of the first transistor (DTr) is electrically connected to an anode electrode of the light emitting element (E) and electrically connected to one of the first electrode and the second electrode of the first capacitive element (StgC).
As to claim 36, Ryu teaches Figure 2 shows a first terminal of the second transistor (Str) is directly connected to another one of the first electrode and the second electrode of the first capacitive element (StgC).
As to claim 37, Ryu teaches Figure 2 shows the gate electrode of the first transistor (DTr) is directly connected to the first terminal of the second transistor (STr).
As to claim 38, Ryu teaches Figure 2 shows a second terminal of the first transistor (DTr) is electrically connected to a power supply line (PL), and a second terminal of the second transistor (Str) is electrically connected to a signal line (DL), and a gate electrode of the second transistor (STr) is electrically connected to a scanning line (GL).
As to claim 40, Ryu teaches Figure 2 shows the first transistor is a drive transistor (DTr), and the second transistor is a writing transistor (STr).
As to claim 41, Ryu teaches Figure 3 shows a top surface of the first electrode (106) of the first capacitive element (StgC) is below a bottom surface of the gate electrode (120b) of the first transistor (DTr) in the cross-sectional view.
As to claim 42, Ryu teaches Figure 3 shows the first electrode (106) of the first capacitive element (StgC) is on a different layer from the gate electrode (120b) of the first transistor (DTr).
Claim(s) 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Jintyou as applied to claim 1 above, and further in view of Koo et al. US 2004/0169182.
As to claims 24-25, Ryu and Jintyou fail to teach the first transistor and the second transistor are different in carrier mobility and a first carrier mobility of the first transistor is lower than a second carrier mobility of the second transistor.
Koo teaches a light emitting device (an organic EL display device 100, see ¶27, and Fig 1); a light emitting element (an organic EL element 160, see ¶27); a first transistor (a drive transistor 145, ¶28); a second transistor (a switching transistor 140, ¶28); a capacitive element (a capacitor 150, ¶28); the first transistor and the second transistor are different in carrier mobility (Koo's Par. 36-37 explained the driving transistor and the switching transistor have different mobilities, and the switching transistor 140 has a higher mobility than that of the driving transistor 145.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the switching transistor 140 has a higher mobility than that of the driving transistor 145, as Koo teaches, to modify the first and second transistors of Ryu. The motivation for doing so would improve reliability by controlling an amount of current flowing to an EL device while providing a high frequency transistor having a high mobility required in circuit mounting and a transistor having a low mobility for reducing an amount of current flowing to the EL device. See Koo ¶56-¶57.
Claim(s) 28-29 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Jintyou as applied to claim 1 above, and further in view of Minami et al. (US 2012/0327058).
As to claim 28, Ryu and Jintyou fail to teach the second transistor is an MOS transistor.
As to claim 39, Ryu and Jintyou fail to teach a second capacitive element directly connected to the first capacitive element.
Minami modified teaches the light emitting device having the first transistor is an n-channel type MOS transistor. (See Minami ¶93).
Figure 4 of Minami teaches a second capacitor Cel directly connected to the first capacitor Ccs.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the first transistor is an n-channel type MOS transistor, the second capacitor Cel connected to the first capacitor Ccs, as Minami teaches, to modify the first transistor of Ryu and Jintyou. The motivation for doing so would have been to suppress the luminance change due to the resistance component between the reference electric potential point and the display element by controlling the characteristics of the drive transistor. See Minami ¶12.
As to claim 29, Figure 3 of Ryu shows the second transistor (Str) is disposed on the silicon substrate (101).
Claim(s) 30, 32, 34 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Jintyou as applied to claim 1 above, and further in view of Yamashita et al. US 2015/0349005.
As to claim 30, Ryu and Jintyou fail to teach the first capacitive element is a Metal-Insulator-Metal (MIM) capacitor.
As to claim 32, Ryu and Jintyou fail to teach the first capacitive element is a Metal-Insulator-Semiconductor (MIS) capacitor.
As to claim 34, Ryu and Jintyou fail to teach a gate oxidized film thickness of the second transistor and an insulator film thickness of the first capacitive element are different.
Yamashita teaches a metal-insulator-metal capacitor having the first metal line 117a and the second metal line 117b. See ¶ 55.
Yamashita teaches a metal-insulator-metal (MIS) capacitor 117. See Yamashita ¶26 and Fig 10.
Yamashita in ¶45, ¶55, and Fig 10 explained the MIS capacitor 117 and the gate oxide of transistor 115 has thickness different.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the metal-insulator-metal capacitor having the first metal line 117a and the second metal line 117b, the MIS capacitor 117 and the gate oxide of transistor 115 has thickness different, as Yamashita teaches, to modify Ryu and Jintyou. The motivation for doing so would have been to reduce the thickness of the display device, minimize the parasitic capacitance, and reduce power consumption. See Yamashita ‘005 ¶23.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Jintyou as applied to claim 30 above, and further in view of Yamazaki et al. (US 2014/0008647).
As to claim 31, Ryu and Jintyou fail to teach the first capacitive element is located between the first transistor and the second transistor in the cross-sectional view.
Yamazaki teaches the capacitor 693 was located between the first transistor 740 and the second transistor 610. See Figure 5A.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the capacitor 693 was located between the first transistor 740 and the second transistor 610, as Yamazaki teaches, to modify Ryu. The motivation for doing so would have been to improve high speed operation and the field effect mobility of the transistor. Yamazaki ¶182, ¶222.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu, Jintyou and Yamashita as applied to claim 32 above, and further in view of Song et al. US 2016/0055976.
Ryu, Jintyou and Yamashita fail to teach the second electrode of the first capacitive element is a portion of the substrate.
Song teaches a capacitor 104 including the second electrode 302 embedded within a portion of the substrate 102. Song ¶ 33-36, Figs 1-4.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the capacitor 104 including the second electrode 302 embedded within the portion of the substrate 102, as Yamazaki teaches, to modify Ryu, Jintyou and Yamashita. The motivation for doing so would have been to suppresses variations of the power supply voltage and the inter-circuit interference. Song ¶ 2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Nguyen whose telephone is 571-272-7697. The examiner can normally be reached M-F 8am-5pm Eastern Time.
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KEVIN M NGUYEN
Patent Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628
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