DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-8, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakurai et al. (US 2020/0135400).
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Regarding claim 1, Sakurai et al. disclose in fig. 1C, a multilayer ceramic electronic component [0001], comprising:
a dielectric (4) including a first surface (4d), a second surface (4c) opposite the first surface (4d), and side surfaces (4a, 4b) connecting the first surface (4d) and the second surface (4c), the dielectric including a plurality of stacked dielectric layers (10);
an internal electrode (12) in the dielectric (4);
an external electrode (52) penetrating the dielectric (10) and the internal electrode (52); and
a molding layer (18, 19 – [0095], [0110]) covering the first surface (4d) of the dielectric (4) and the side surfaces (4a, 4b) of the dielectric,
wherein the second surface (4c) of the dielectric (4) is at a different level than or at a same level as a lower surface of the molding layer (18,19).
Regarding claim 2, Sakurai et al. disclose a connection pad (6 – [0054] – lowermost layer of the multilayer structure) on the second surface (4c) of the dielectric (4); and a connection terminal (6 – [0054] uppermost layer of the multilayer structure) on the connection pad.
Regarding claim 3, Sakurai et al. disclose the connection pad (6) is closer to the dielectric (4) than the molding layer (18) in a vertical direction (@4c).
Regarding claim 4, Sakurai et al. disclose the connection pad (6) and the molding layer (18, 19) do not contact each other.
Regarding claim 5, Sakurai et al. disclose a lower surface of the external electrode (52) is at a same level as the second surface (4c) of the dielectric (4).
Regarding claim 7, Sakurai et al. disclose the dielectric (4) includes at least one of barium titanate or strontium titanate [0123], and wherein the internal electrode, the external electrode, or both the internal electrode and the external electrode include at least one of nickel [0124], copper [0135], and palladium.
Regarding claim 8, Sakurai et al. disclose at least one end of the external electrode (52) contacts (at least indirectly) the molding layer (19).
Regarding claim 13, Sakurai et al. disclose a multilayer ceramic electronic component [0001], comprising:
a dielectric (4) including a plurality of stacked dielectric layers (10);
an internal electrode (12) in the dielectric (4);
an external electrode (52) penetrating the dielectric (4) and the internal electrode (12);
a connection pad (6) on the external electrode (52); and
a molding layer (18, 19) on a plurality of surfaces of the dielectric (4),
wherein the connection pad (6) and the molding layer (18, 19) are spaced apart from each other, and
wherein at least one surface (4c) of the plurality of surfaces of the dielectric (4) does not include the molding layer (18, 19).
Claim(s) 1, and 9-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (KR 20140011765A).
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Regarding claim 1, Kang et al. disclose in fig. 1C, a multilayer ceramic electronic component, comprising:
a dielectric (50) including a first surface (bottom), a second surface (top) opposite the first surface (bottom), and side surfaces (left-right) connecting the first surface (bottom) and the second surface (top), the dielectric (50) including a plurality of stacked dielectric layers (50);
an internal electrode (30) in the dielectric (50);
an external electrode (70) penetrating the dielectric (50) and the internal electrode (30); and
a molding layer (80, Translation - P:5, P: 1) covering the first surface (bottom) of the dielectric (50) and the side surfaces (left-right) of the dielectric (50),
wherein the second surface (top) of the dielectric (50) is at a different level than or at a same level as a lower surface of the molding layer (80).
Applicant should note the term “cover” does not mean “in direct physical contact with”.
Regarding claim 9, Kang et al. disclose a protective layer (60) on the second surface (top),
wherein a lower surface of the protective layer (60) is at a same level as a lower surface of the molding layer (80).
Regarding claim 10, Kang et al. disclose the protective layer (60) includes at least one of silicon nitride (translation P: 5, P: 1) or silicon oxide.
Regarding claim 11, Kang et al. disclose the external electrode (70) penetrates the protective layer (60).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai et al. (US 2020/0135400).
Regarding claim 6, Sakurai et al. disclose the thickness of the molding layer has to be less than 100 µm [0014].
Sakurai et al. disclose the claimed invention except for the molding layer has a thickness of 1 µm to 100 µm.
A reinforcing layer having a thickness of 1 to 100 µm is well known in the art.
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the device of Sakurai et al. so that the molding layer has a thickness of 1 µm to 100 µm, since such a modification would form a multilayer ceramic capacitor having desired robustness while having a low-thickness profile.
Regarding claim 14, Sakurai et al. disclose the invention is not limited to the embodiments as disclosed [0117], [0121].
Sakurai et al. disclose the claimed invention except for a specific example where the component further comprises a protective layer on a lower surface of the dielectric, wherein the connection pad contacts the external electrode and the protective layer.
Sakurai et al. disclose an embodiment wherein the component (Fig.1B) comprises a protective layer (16) on a lower surface of the dielectric (4), wherein the connection pad (6, 8) contacts the external electrode (52).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor of Sakurai et al. so that Fig. 1C includes a protective layer on a lower surface of the dielectric, wherein the connection pad contacts the external electrode and the protective layer, since such a modification would form a capacitor having increased strength.
Regarding claim 15, the modified Sakurai et al. disclose an upper surface of the protective layer (16) is at a higher level than a lower surface of the molding layer (18, 19).
Regarding claim 16, the modified Sakurai et al. disclose the molding layer (18, 19) contacts (at least in direct contact with) side surfaces of the protective layer (16).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (KR 20140011765A).
Regarding claim 12, Kang et al. disclose a connection pad (71) on the protective layer (60).
Kang et al. disclose the claimed invention except for a connection terminal on the connection pad.
It is well known in the electrical connection art to form a connection terminal (solder bump, adhesive, etc.) on a connection pad.
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor of Kang et al. so that a connection terminal is formed on the connection pad, since connectors are selected based on design considerations and tradeoffs between cost, mechanical properties, and electrical properties.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakurai et al. (US 2020/0135400) in view of Kikuchi et al. (US 2002/0171153).
Regarding claim 17, Sakurai et al. disclose a multilayer ceramic electronic component includes:
a dielectric (4) including a plurality of stacked dielectric layers (10);
an internal electrode (12) in the dielectric (4);
an external electrode (52) penetrating the dielectric (10) and the internal electrode (12);
a connection pad (6 – [0054] – lowermost layer of the multilayer structure) external electrode (52) and the dielectric (10);
a connection terminal (6 – [0054] uppermost layer of the multilayer structure) on the connection pad; and
a molding layer (18, 19) on the dielectric (4), and
wherein the molding layer (18, 19) covers a plurality of surfaces of the dielectric (4) except for a surface including the connection pad (6).
Sakurai et al. disclose the claimed invention except for an electronic device, comprising a package substrate; and a semiconductor chip and the multilayer ceramic electronic component on the package substrate and spaced apart from each other in a first direction parallel to an upper surface of the package substrate.
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Kikuchi et al. disclose in fig. 5, an electronic device, comprising a package substrate (113); and a semiconductor chip (140, [0068]) and a multilayer ceramic electronic component (120, [0068]) on the package substrate (113) and spaced apart from each other in a first direction parallel to an upper surface of the package substrate (13).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the multilayer ceramic capacitor of Sakurai et al. on a package substrate, wherein a semiconductor chip and the multilayer ceramic electronic component are formed on the package substrate and spaced apart from each other in a first direction parallel to an upper surface of the package substrate, since such a modification would form an electronic device having a multilayer capacitor that has a low profile and mechanically robust.
Regarding claim 18, Sakurai et al. disclose the thickness of the molding layer has to be less than 100 µm [0014].
Sakurai et al. disclose the claimed invention except for the molding layer has a thickness of 1 µm to 100 µm.
A reinforcing layer having a thickness of 1 to 100 µm is well known in the art.
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the device of Sakurai et al. so that the molding layer has a thickness of 1 µm to 100 µm, since such a modification would form a multilayer ceramic capacitor having desired robustness while having a low-thickness profile.
Regarding claim 19, Sakurai et al. disclose the multilayer ceramic electronic component further includes a plurality of external electrodes (52, 52) in the first direction (left-right) and in a second direction parallel to the upper surface of the package substrate, and wherein the second direction is perpendicular to the first direction.
Regarding claim 20, Sakurai et al. disclose the dielectric (10) includes at least one of barium titanate or strontium titanate [0123], and wherein the internal electrode, the external electrode, or both the internal electrode and the external electrode include at least one of nickel, copper, and palladium [0124], [0135].
Conclusion
Applicant is encourage to contact the examiner to discuss possible amendments to overcome the current rejection of record. The examiner can normally be reached Monday-Friday, 6:00 AM-2:30 PM.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2018/0068796
US 2018/0068793
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC THOMAS whose telephone number is (571)272-1985. The examiner can normally be reached Monday-Friday, 6:00 AM-2:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W THOMAS/Primary Examiner, Art Unit 2847
ERIC THOMAS
Primary Examiner
Art Unit 2847
