DETAILED ACTION
I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) is acknowledged.
III. Claim Objections
Claim 11 is objected to because of the following informalities:
A. On line 16, the indentation of the color filter array clause should be changed so that the imaging system comprises the color filter array. As currently drafted, the claim appears to require that each pixel includes a color filter array, which the examiner believes is not the intended scope of each pixel.
B. On line 29, the examiner suggests inserting “switch” between “mode select” and “circuit.”
IV. Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3,10-13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Suh et al. (US 2020/0084403 A1) in view of
Zhao et al. (US 2025/0209572 A1)
As to claim 1, Suh et al. teaches a pixel circuit (Fig. 1, pixel array “1210” and color filter
array discussed in [0117], lines 2-10), comprising:
a pixel array (Fig. 2, pixel array “1210”) including a plurality of pixels arranged in rows and columns ([0046], lines 1 and 2), wherein each pixel (Fig. 7; {The examiner reads a claimed pixel as a two CIS “pixels” arranged in the same row and sharing a floating diffusion node. Note, particularly, [0046], lines 9-12.}) includes:
a first photodiode (Fig. 7, photoelectric conversion device “PSD”) configured to photogenerate a first image charge in response to incident light ([0055], lines 1-3);
a second photodiode (Fig. 7, a row-adjacent photoelectric conversion device “PSD”) configured to photogenerate a second image charge in response to incident light ([0055], lines 1-3);
a floating diffusion (e.g., Fig. 9, floating diffusion region “FD”) coupled to receive the first image charge from the first photodiode and receive the second image charge from the second photodiode ([0056], lines 1-3; note, again [0046], lines 9-12);
a first transfer transistor (e.g., Fig. 9, transfer transistor “TG”) coupled between the first photodiode and the floating diffusion to transfer the first image charge from the first photodiode to the floating diffusion ([0056], lines 1-3); and
a second transfer transistor (e.g., Fig. 9, a row-adjacent transfer transistor “TG”) coupled between the second photodiode and the floating diffusion to transfer the second image charge from the second photodiode to the floating diffusion ([0056], lines 1-3); and
a color filter array disposed over the pixel array, wherein the color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels (e.g., [0117], lines 2-10),
wherein each of the plurality of pixels is selectively coupled ([0109]) to a first readout circuit (Fig. 2, CDS “1230,” ADC “1240,” and output buffer “1250”), and
wherein each of the plurality of pixels is selectively coupled ([0099]) to a second readout circuit (Fig. 6, readout circuit “1318”; [0076], lines 1 and 2).
Suh et al. discloses that all of the pixels of the pixel array either operate in a first mode, when all pixels are used to produce a normal image, or operate in a second mode, when all pixels are used to produce DVS or event data. That is, the reference fails to specifically disclose (1) that the plurality of pixels includes a first subset of the pixels configured to be disconnected from the second readout circuit while connected to the first readout circuit to read out a first set of data signals and a second subset of the pixels selectively coupled to the second readout circuit to read out a second set of data signals, (2) that the second set of data signals is different from the first set of data signal, (3) that each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels, and (4) that the first pixel and the second pixel are disposed underneath one of the color filters.
However, in the same field of endeavor as the instant application, Zhao et al. teaches an image sensor (Figs. 1 and 2) with a plurality of hybrid pixels that outputs both event information and normal imaging information (Figs, 1 and 2, APS pixels “A” and EVS pixels “E”) and that is interspersed within a common array ([0062] and [0063]). The image sensor operates in a first mode in which all of the pixels output temporally-multiplexed event information and normal imaging information (Fig. 1; [0065], lines 1-5) or in a second mode in which some pixels output event information and some pixels output normal imaging information (2) (Fig. 2; [0067], lines 1-5). In the second mode, the event pixels and normal imaging pixels are arranged in a checkerboard pattern (Fig. 2; [0067], lines 5-16; {The claimed first subset includes the normal imaging/APS pixels and the claimed second subset includes event pixels.}), where the event pixels include a pixel arranged in a first row and the normal imaging pixels include a pixel arranged in a row adjacent to the first row (3) (Fig. 2), and are selectively connected to one of an event pixel read-out circuit (Fig. 6, EVS readout “62”; [0105]) or a normal imaging read-out circuit (1) (Fig. 6, APS readout “61”; [0104], lines 1 and 2). Moreover, normal imaging pixels are covered by one of a red, green, or blue color filter ([0068], lines 1 and 2; note, also, Fig. 3), and event pixels do not receive specific color information (4) (i.e., are “covered” by a clear filter) ([0068], line 3; note, also, [0104], lines 2-10).
In light of the teaching of Zhao et al., the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to modify Suh’s read-out scheme to include a mode in which a first subset of pixels outputs CIS information and a second subset outputs event information, where the first and second subsets are arranged within the pixel array in a checkerboard pattern, event information is routed to the DVS read-out circuit “1318,” and normal imaging information is routed to the CDS, ADC, and output buffer through a timing control scheme for closing switch “SW1” or switch “SW2” of Suh’s Fig. 9. Additionally, the examiner submits that it would have been obvious to one of ordinary skill in the art to place normal imaging pixels under an RGB color filter pattern as illustrated by Zhao et al. and design DVS/event pixels as clear pixels. One of ordinary skill in the art would recognize that supplementing Suh’s system with this additional spatial multiplexing scheme would allow for event information and normal image information to be captured simultaneously, thereby increasing the efficiency of information capture. Furthermore, by placing the normal imaging pixels under color filters, color information can be obtained to improve the image quality, and by designing the event pixels as clear pixels, event information with a high signal-to-noise ratio can be obtained to increase the fidelity of the event detection process.
As to claim 2, Suh et al., as modified by Zhao et al., teaches the pixel circuit of claim 1, wherein the second subset of the pixels comprises 50% of the pixels included in the pixel array (see Zhao et al., Fig. 2; [0067], lines 7-9).
As to claim 3, Suh et al., as modified by Zhao et al., teaches the pixel circuit of claim 1, further comprising a plurality of microlenses disposed over the pixel array, wherein each microlens is disposed over each pixel (see Suh et al., Fig. 8, lenses “1201”; [0082], lines 3 and 4).
As to claim 10, Suh et al., as modified by Zhao et al., teaches the pixel circuit of claim 1, wherein each 2×2 grouping of pixels arranged in two adjacent rows and two adjacent columns includes a first pair of pixels included in the second subset of the pixels (see Zhao et al., Fig. 2, APS pixels “E”) and a second pair of pixels included in the first subset of the pixels (Fig. 2, diagonal APS pixels “A”) and disposed underneath two of the color filters ([0068], lines 1 and 2).
As to claim 11, Suh et al. teaches an imaging system (Fig. 1, image sensor “1000”),
comprising:
a pixel circuit including a pixel array (Fig. 2, pixel array “1210”) having a plurality of pixels arranged in rows and columns ([0046], lines 1 and 2), wherein each pixel (Fig. 7; {The examiner reads a claimed pixel as a two CIS “pixels” arranged in the same row and sharing a floating diffusion node. Note, particularly, [0046], lines 9-12.}) includes:
a first photodiode (Fig. 7, photoelectric conversion device “PSD”) configured to photogenerate a first image charge in response to incident light ([0055], lines 1-3);
a second photodiode (Fig. 7, a row-adjacent photoelectric conversion device “PSD”) configured to photogenerate a second image charge in response to incident light ([0055], lines 1-3);
a floating diffusion (e.g., Fig. 9, floating diffusion region “FD”) coupled to receive the first image charge from the first photodiode and receive the second image charge from the second photodiode ([0056], lines 1-3; note, again [0046], lines 9-12);
a first transfer transistor (e.g., Fig. 9, transfer transistor “TG”) coupled between the first photodiode and the floating diffusion to transfer the first image charge from the first photodiode to the floating diffusion ([0056], lines 1-3); and
a second transfer transistor (e.g., Fig. 9, a row-adjacent transfer transistor “TG”) coupled between the second photodiode and the floating diffusion to transfer the second image charge from the second photodiode to the floating diffusion ([0056], lines 1-3); and
[ ]a color filter array disposed over the pixel array, wherein the color filter array
includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels (e.g., [0117], lines 2-10);
a first readout circuit (Fig. 2, CDS “1230,” ADC “1240,” and output buffer “1250”) selectively coupled to each of the plurality of pixels to read out a first set of data signals ([0076], lines 1 and 2);
a second readout circuit (Fig. 6, readout circuit “1318”); and
a mode select switch circuit (Fig. 9, switches “SW1” and “SW2”) coupled to the plurality of pixels ([0091]).
Suh et al. discloses that all of the pixels of the pixel array either operate in a first mode,
when all pixels are used to produce a normal image, or operate in a second mode, when all pixels are used to produce DVS or event data. That is, the reference fails to specifically disclose (1) that the plurality of pixels includes a first subset of the pixels configured to be disconnected from the second readout circuit while coupled to the first readout circuit and a second subset of the pixels selectively coupled to the second readout circuit, (2) that the second readout circuit is coupled to each of the pixels included in the second subset to read out a second set of data signals, (3) that the mode select switch circuit is coupled to the pixels included in the second subset, (4) that the pixels included in the second subset are configured to provide either the first set of data signals to the first readout circuit or the second set of data signals to the second readout circuit in response to the mode select circuit, (5) that each pair of pixels arranged in two adjacent rows includes a first pixel included in the second subset of the pixels and a second pixel included in the first subset of the pixels, and (6) that the first pixel and the second pixel are disposed underneath one of the color filters.
However, in the same field of endeavor as the instant application, Zhao et al. teaches an image sensor (Figs. 1 and 2) with a plurality of hybrid pixels that outputs both event information and normal imaging information (4) (Figs, 1 and 2, APS pixels “A” and EVS pixels “E”) and that is interspersed within a common array ([0062] and [0063]). The image sensor operates in a first mode in which all of the pixels output temporally-multiplexed event information and normal imaging information (Fig. 1; [0065], lines 1-5) or in a second mode in which some pixels output event information and some pixels output normal imaging information (2) (Fig. 2; [0067], lines 1-5). In the second mode, the event pixels and normal imaging pixels are arranged in a checkerboard pattern (Fig. 2; [0067], lines 5-16; {The claimed first subset includes the normal imaging/APS pixels and the claimed second subset includes event pixels.}), where the event pixels include a pixel arranged in a first row and the normal imaging pixels include a pixel arranged in a row adjacent to the first row (5) (Fig. 2), and are selectively connected to one of an event pixel read-out circuit (Fig. 6, EVS readout “62”; [0105]) or a normal imaging read-out circuit (1) (Fig. 6, APS readout “61”; [0104], lines 1 and 2). Moreover, normal imaging pixels are covered by one of a red, green, or blue color filter ([0068], lines 1 and 2; note, also, Fig. 3), and event pixels do not receive specific color information (6) (i.e., are “covered” by a clear filter) ([0068], line 3; note, also, [0104], lines 2-10).
In light of the teaching of Zhao et al., the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to modify Suh’s read-out scheme to include a mode in which a first subset of pixels outputs CIS information and a second subset outputs event information, where the first and second subsets are arranged within the pixel array in a checkerboard pattern, event information is routed to the DVS read-out circuit “1318,” and normal imaging information is routed to the CDS, ADC, and output buffer through a timing control scheme for closing switch “SW1” or switch “SW2” of Suh’s Fig. 9 (3). Additionally, the examiner submits that it would have been obvious to one of ordinary skill in the art to place normal imaging pixels under a color filter pattern as illustrated by Zhao et al. and design DVS/event pixels as clear pixels. One of ordinary skill in the art would recognize that supplementing Suh’s system with this additional spatial multiplexing scheme would allow for event information and normal image information to be captured simultaneously, thereby increasing the efficiency of information capture. Furthermore, by placing the normal imaging pixels under color filters, color information can be obtained to improve the image quality, and by designing the event pixels as clear pixels, event information with a high signal-to-noise ratio can be obtained to increase the fidelity of the event detection process.
The limitations of claims 12,13, and 20 can be found in claims 2,3, and 10,
respectively, and are, therefore, rejected as detailed above.
B. Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Suh et al. (US 2020/0084403 A1) in view of Zhao et al. (US 2025/0209572 A1) and further in view of Lee et al. (US 2023/0217119 A1)
As to claim 4, Suh et al., as modified by Zhao et al., teaches the pixel circuit of claim 1, further comprising a plurality of microlenses disposed over the pixel array (see Suh et al., Fig. 8, lenses “1201”; [0082], lines 3 and 4). The claim differs from Suh et al., as modified by Zhao et al., in that it requires that each microlens is disposed over a pair of pixels in two adjacent rows. However, in the same field of endeavor as the instant application, Lee et al. discloses an image sensor (Fig. 10, image sensor “1100”) with a plurality of pixels (Fig. 10, pixels array “1110”) and a plurality of microlens, each covering two pixels in adjacent rows (Fig. 10; [0066], lines 1-3). In light of the teaching of Lee et al., the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to design each microlens of Suh et al., as modified by Zhao et al., to cover two pixels in adjacent rows because one of ordinary skill in the art would recognize this modification to be a simple design substitution that would yield a predictable result, where light is condensed onto two row-adjacent pixels rather than a single pixel. Moreover, microlenses of this sort can be fabricated using known techniques, like that used in Lee et al., and can be applied to Suh’s pixel array without detracting from Suh’s goal of developing an image sensor with reduced size and cost. See MPEP 2143 (I)(B) for more information regarding the examiner’s rationale for combining Suh et al. and Lee et al.
The limitations of claim 14 can be found in claim 4 and is, therefore, rejected as detailed
above.
C. Claims 5,6,15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Suh et al. (US 2020/0084403 A1) in view of Zhao et al. (US 2025/0209572 A1) in view of Hunt et al. (US 2025/0016465 A1) and further in view of Wang et al. (US # 12,101,563 B2)
As to claim 5, Suh et al., as modified by Zhao et al., teaches the pixel circuit of claim 1,
wherein the pixels included in the second subset are arranged in a checkerboard pattern across the pixel array (see Zhao et al., Fig. 2; [0067], lines 5-16). The claim differs from Suh et al., as modified by Zhao et al., in that it requires (1) that the color filter array comprises a quad Bayer filter, (2) that each color filter is disposed over a pair of pixels in two adjacent rows, and (3) that color filters of a same color are disposed over a 4x2 grouping of pixels arranged in four adjacent rows and two adjacent columns.
However, in the same field of endeavor as the instant application, Hunt et al. discloses an image sensor (Fig. 2a, image sensor “200”) with a plurality of imaging pixels (Fig. 2a, synchronous pixels “211,223”) and a plurality of hybrid pixels (Fig. 2a, hybrid second pixels “221,222”) that operates as either imaging pixels or event pixels (e.g., [0048], lines 1-4; [0080], lines 1-5). The hybrid pixels can be covered with one of a red, blue, or green color filter ([0076], lines 1-5; [0077]). Further in the same field of endeavor as the instant application, Wang et al. discloses an image sensor with a quad color filter array (RGGB) positioned over sensor pixels in a Bayer pattern (1) (Fig. 3D). Specifically, each color filter is disposed over a pair of pixels in adjacent rows, and same-color filters are contiguously arrayed in a 4x4 pattern (2), (3) (Fig. 3D; col. 15, line 59 – col. 16, line 5; {A 4x4 array includes a 4x2 array.}).
In light of the teaching of Hunt et al. and Wang et al., the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to, rather than position event pixels under a clear filter as disclosed by Suh et al., as modified by Zhao et al., position those event pixels under red, green, and/or blue color filters as disclosed by Hunt et al. and pattern the red, blue, and green color filters over all pixels of the image sensor of Suh, as modified by Zhao et al. in the manner illustrated by Wang et al. in Fig. 3D. One of ordinary skill in the art would recognize that forming a color filter array over all pixels of the array of Suh et al., as modified by Zhao et al., would ensure that color information is captured at each pixel location when the image sensor operates in Suh’s first mode, thereby alleviating he need interpolate missing color data. Furthermore, Wang’s pattern of a plurality of contiguous 4x4 arrays would allow the image sensor to adjust exposure time at different pixel positions (see Wang et al., col. 14, lines 47-67) and/or bin same-color pixels to provide an image with increased sensitivity (see Wang et al., col. 14, lines 24-46).
The combination Suh et al., Zhao et al., and Wang et al. detailed above in claim 5 forms the basis for the rejection of claim 6 that follows.
As to claim 6, Suh et al., as modified by Zhao et al., Hunt et al., and Wang et al., teaches the pixel circuit of claim 1, wherein the color filter array comprises a quad Bayer filter array such that (i) each color filter is disposed over a pair of pixels in two adjacent rows and (ii) color
filters of a same color are disposed over a 4x2 grouping of pixels arranged in four adjacent rows and two adjacent columns (See cited passages of Hunt et al. and Wang et al. above), and wherein the pixels included in the second subset are arranged in alternating rows across the pixel array (see Zhao et al., Fig. 2; [0067], lines 5-16; {The examiner submits that a checkerboard pattern of event pixels encompasses a pattern in which event pixels are arranged in alternating rows (i.e., odd or even rows). That is, simply reciting that second subset pixels are in alternating rows does not mean that second subset pixels cannot be in adjacent rows.}).
The limitations of claims 5 and 6 can be found in claims 15 and 16, respectively, and are,
therefore, rejected as detailed above.
D. Claims 7,8,17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Suh et al. (US 2020/0084403 A1) in view of Zhao et al. (US 2025/0209572 A1) in view of Sato et al. (US 2025/0159374 A1)
As to claim 7, Suh et al., as modified by Zhao et al., teaches the pixel circuit of claim 1,
wherein clear filters are disposed over the pixels included in the second subset and arranged in a checkerboard pattern across the pixel array (see Zhao et al., Fig. 2; [0067], lines 5-16; [0104], lines 9 and 10). The claim differs from Suh et al., as modified by Zhao et al., in that it requires (1) that the color filter array comprises a quad color filter array formed of red (R) color filters, green (G) color filters, and blue (B) color filters, and an array of clear (C) filters such that (2) RGB filters of a same color are disposed over four pixels included in the first subset arranged in a zigzag manner in four adjacent rows and two adjacent columns.
However, in the same field of endeavor as the instant application, Sato et al. discloses an image sensor (Fig. 1, imaging element “1”) having an RGBW color filter array over sensor pixels (1) (Fig. 20B). White filters are arranged in a checkerboard pattern across the sensor pixel array (Fig. 20B, white pixels “W”), and eight same-color RGB filters are positioned in a zigzag manner over a contiguous 4x4 array of pixels (2) (Fig. 20B; {Eight pixels in 4x4 array includes four pixels in a 4x2 array.}). In light of the teaching of Sato et al., the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to position red, green, and blue color filters over the imaging pixels of Suh et al., as modified by Zhao et al., because this pattern would allow for the capture of color information with an increased signal-to-noise ratio by adding white pixel signals to the red, green, and blue pixel signals, which would be particularly beneficial when Suh’s sensor operates in the first mode in a dark environment (see Sato et al., [0004] and [0065]).
The combination Suh et al., Zhao et al., and Sato et al. detailed above in claim 7 forms the basis for the rejection of claim 8 that follows.
As to claim 8, Suh et al., as modified by Zhao et al., and Sato et al., teaches the pixel circuit of claim 1, wherein the color filter array comprises a quad RGBC filter array formed of red (R) color filters, green (G) color filters, blue (B) color filters, and clear (C) filters such that (i) RGB filters of a same color are disposed over four pixels included in the first subset arranged in two non-adjacent rows and two adjacent columns (see Sato et al., Fig. 20B; {In Sato’s Fig. 3, the four red pixels are a first red pixel in the first row/first column, a second red pixel in the fourth row/second column, a third pixel in the first row/third column, and a fourth pixel in the fourth row/fourth column. This pattern extends over two non-adjacent rows and four adjacent columns, which includes two adjacent columns. Also, this pattern is repeated for the blue and green pixels as illustrated in Sato’s Fig. 20B.}), and (ii) clear filters are disposed over the pixels included in the second subset and arranged in alternating rows across the pixel array (see Zhao et al., Fig. 2; [0067], lines 5-16; [0104], lines 9 and 10; {The examiner submits that a checkerboard pattern of event pixels encompasses a pattern in which event pixels are arranged in alternating rows (i.e., odd or even rows). That is, simply reciting that second subset pixels are in alternating rows does not mean that second subset pixels cannot be in adjacent rows.}).
The limitations of claims 7 and 8 can be found in claims 17 and 18, respectively, and are,
therefore, rejected as detailed above.
E. Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Suh et al. (US 2020/0084403 A1) in view of Zhao et al. (US 2025/0209572 A1) in view of Hirota (US 2010/0141812 A1)
As to claim 9, Suh et al., as modified by Zhao et al., teaches the pixel circuit of claim 1. The claim differs from Suh et al., as modified by Zhao et al., in that it requires (1) that the color filter array comprises a color filter array formed of red (R) color filters, green (G) color filters, blue (B) color filters, and clear (C) filters such that (i) RGB filters of different colors are disposed over pixels included in the first subset arranged in adjacent columns and (2) clear filters are disposed over the pixels included in the second subset and arranged in alternating rows across the pixel array.
However, in the same field of endeavor as the instant application, Hirota teaches an image sensor (Fig. 1, image sensor “10”) having an RGBW color filter array over sensor pixels (Fig. 10). White filters are arranged in alternating rows across the sensor pixel array (Fig. 10, white pixels “W”), and differently-colored RGB filters are positioned along adjacent columns (Fig. 10; {For example, red, blue, and green filters are arranged in the first three adjacent columns.}). In light of the teaching of Sato et al., the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application use Hirota’s color filter pattern on the pixel array of Suh et al., as modified by Zhao et al., where white filters are positioned over event pixels, because this pattern would allow for an increase in color information capture in Suh’s first mode by replacing half of the clear filters with a designated RGB filter.
The limitations of claim 19 can be found in claim 9 and is, therefore, rejected as detailed
above.
V. Additional Pertinent Prior Art
Oyama et al. (US 2025/0008236 A1), Yorikado (WO 2024/127912 A1), and Takao et al. (WO 2021/159231 A1) each disclose additional examples of a hybrid image sensor with both event and imaging pixels in its array.
VI. Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY J DANIELS whose telephone number is (571)272-7362. The examiner can normally be reached M-F 9:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY J DANIELS/Primary Examiner, Art Unit 2637
1/16/2026