DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed on October 17, 2024 have all been considered and made of record (note the attached copy of form PTO-1449).
Drawings
Fifteen (15) sheets of drawings were filed on October 17, 2024 and have been accepted by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2021/0096310 A1) in view of Yu et al. (US 2020/0003975 A1).
Regarding claim 1; Chang et al. (US 2021/0096310 A1) discloses a semiconductor package (package assembly 10, 40; see Figures 1B and 4B) comprising:
an interposer substrate (300; 300’; see paragraphs 43 and 61, wherein 300, 300’ may be a package substrate or an interposer); and
a photonics chip structure (100A/200A) mounted on the interposer substrate (300, 300’),
wherein the photonics chip structure (100A, 200A) comprises:
an electronic integrated circuit portion (ED: 131, 132, 133, 134, 135 & 170: 172, 174) including an electronic integrated circuit chip (electronic die, ED, 131) mounted on the interposer substrate (300, 300’);
an optical integrated circuit portion (PD: 111, 112, 113, 114, 115) including
an optical integrated circuit chip (PD die 111) mounted on the electronic integrated circuit chip (see Figures 1B and 4B),
an edge coupler (the PDs are edge coupled to fibers 210, thus the edge of the PDs form an edge coupler), and
a waveguide connected to the edge coupler (Chang teaches that the active layer of photonic PD die may include a waveguide); and
a connector (optical fiber, 210, provides optical connection) facing the edge coupler.
Chang et al. does not disclose:
a package substrate below the interposer (300, 300’)
a groove at a corner of an upper portion of the optical integrated circuit chip,
the edge coupler extending toward the groove, and
a glass connector mounted in the groove of the optical integrated circuit portion and facing the edge coupler.
The examiner takes Official notice that it’s elementary in the art to mount an interposer substrate on top of a package substrate.
Yu et al. (US 2020/000975 A1) discloses an optical integrated circuit portion of a semiconductor assembly (see Figure 3K) including an optical integrated circuit chip (photonic integrated circuit die 200) having a groove (300c; material of notch N is removed to expose the groove) at a corner of an upper portion thereof and mounted on an electronic integrated chip (SUB), and edge coupler (200b) extending toward the groove (200c), and a waveguide (see paragraph 20) connected to the edge coupler; and a glass connector (optical fiber; the examiner notes that optical fibers are routinely and commonly made of glass) mounted in the groove (200c) of the optical integrated circuit portion and facing the edge coupler (200b).
Before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to mount the interposer (300, 300’) on a desired package substrate for the purpose of incorporating the assembly into a package for handling and use, as is elementary and routine in the art, wherein no unexpected or novel results or advantages would occur.
Additionally, before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to provide a groove at a corner of the upper portion of the optical integrated circuit chip of Chang et al., wherein the groove is positioned to allow an optical fiber to be stably aligned with the edge coupler of Chang et al. extending towards and facing the groove, and to mount a glass optical fiber in the groove and facing the edge coupler for the purpose of providing a stable support for the coupled tip of the optical fiber to maintain an optimal optical alignment and improve coupling efficiency, since the use of grooves to align coupling elements with edge couplers were known alternatives optical connection arrangements in the prior art and one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding claim 6; The semiconductor package of claim 1, wherein the glass connector includes a protrusion protruding outward from a sidewall of the optical integrated circuit chip (optical fiber, FB of Yu et al./210 of Chang et al.) include a end protruding outward from a sidewall of the optical integrated circuit chip, this including a protrusion)
Regarding claim 7; Chang et al. and Yu et al. teach and/or suggest the semiconductor package of claim 6 as discussed above, including a distance from the sidewall of the optical integrated circuit chip to an outermost portion of the protrusion of the glass connector (fiber, FB of Yu/210 of Chang), but fail to teaches wherein a distance from the sidewall of the optical integrated circuit chip to an outermost portion of the protrusion of the glass connector is in a range of about 0.01 mm to about 100 mm.
Before the effective filing date of the claimed invention, a person of ordinary skill in the art would have found it obvious to provide any desired distance to ensure optimal optical coupling results for the intended use of the device, including a distance in the range of about 0.01 mm to about 100 mm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (In re Aller, 105 USPQ 233), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since such a modification would have involved a mere change in the size of a component and it has been held that a change in size is generally recognized in as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)) and that, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (In re Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 8; Chang et al. further discloses that an area of an upper surface of the optical integrated circuit chip (111) is greater than an area of an upper surface of the electronic integrated circuit chip (131; see Figure 2A of Chang et al.).
Regarding claim 9; Chang et al. further discloses wherein the electronic integrated circuit portion further includes a vertical connection conductor (TSVs 160) surrounding the electronic integrated circuit chip (surrounding a side of the circuit chip 131), and wherein a vertical height of the vertical connection conductor (160) is greater than a vertical height of the electronic integrated circuit chip (131).
Regarding claim 10; Chang et al. further discloses wherein the optical integrated circuit portion further includes a photonics integrated circuit (PIC) insulating layer (113 and/or 115; see Figure 2A of Chang et al.) disposed below the optical integrated circuit chip (111), and a PIC conductive pad (112/114) buried in the PIC insulating layer (113/115), wherein the electronic integrated circuit portion further includes an electronics integrated circuit (EIC) insulating layer (152) disposed below the PIC insulating layer (113/115), and an EIC conductive pad (154) buried in the EIC insulating layer (152), and wherein the PIC insulating layer (113/115) and the PIC conductive pad (112/114) are hybrid-bonded with the EIC insulating layer (152) and the EIC conductive pad (154), respectively (see Figure 2A of Chang et al.).
Regarding claim 11; Chang et al. and Yu et al. teach and/or suggest the semiconductor package of claim 1 as discussed above, but fail to disclose specific dimensions of the photonics chip, thereby suggesting a lack of criticality to the particular size of the photonics chip. Before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to use any desired photonics chip in the assembly of Chang et al. including a photonics chip wherein a vertical height of the photonics chip structure is in a range of about 0.05 mm to about 2 mm, since such a modification would have involved a mere change in the size of a component and it has been held that a change in size is generally recognized in as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)) and that, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (In re Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Allowable Subject Matter
Claims 2-5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2; the prior art of record, which is the most relevant prior art known, does not disclose or render obvious the semiconductor package defined by claim 2, further comprising a dummy chip disposed on the optical integrated circuit portion to face the glass connector in combination with all of the limitations of base claim 1.
Claims 3-5 are allowable by virtue of dependency from claim 2.
Regarding claim 12; the prior art of record, which is the most relevant prior art known, does not disclose or render obvious a semiconductor package as defined by claim 12, comprising:
a package substrate;
an interposer substrate disposed on the package substrate;
a photonics chip structure mounted on the interposer substrate;
a logic chip structure disposed on the interposer substrate and spaced apart from the photonics chip structure in a horizontal direction; and
a memory chip structure disposed to face a side surface of the logic chip structure,
wherein the photonics chip structure comprises:
an electronic integrated circuit portion including
an electronic integrated circuit chip mounted on the interposer substrate;
an optical integrated circuit portion including
an optical integrated circuit chip having a groove at a corner of an upper portion thereof and mounted on the electronic integrated circuit chip,
an edge coupler disposed to correspond to the groove, and
a waveguide connected to the edge coupler;
a glass connector mounted in the groove of the optical integrated circuit portion and facing the edge coupler; and
a dummy chip disposed on the optical integrated circuit portion to face the glass connector.
Claims 13-18 are allowable by virtue of dependency from claim 12.
Regarding claim 19; the prior art of record, which is the most relevant prior art known, does not disclose or render obvious a semiconductor package, as defined by claim 19, comprising:
a package substrate;
an interposer substrate disposed on the package substrate;
a photonics chip structure mounted on the interposer substrate;
a logic chip structure disposed on the interposer substrate and spaced apart from the photonics chip structure in a horizontal direction;
a first memory chip structure disposed to face a first side surface of the logic chip structure; and
a second memory chip structure facing a second side surface opposite to the first side surface and disposed between the photonics chip structure and the logic chip structure,
wherein the photonics chip structure comprises:
a photonics substrate;
an electronic integrated circuit portion including an electronic integrated circuit chip mounted on the photonics substrate;
an optical integrated circuit portion having a groove at a corner of an upper portion thereof and mounted on the electronic integrated circuit chip,
the optical integrated circuit portion including an edge coupler disposed to correspond to the groove and a first waveguide connected to the edge coupler;
a glass connector mounted in the groove of the optical integrated circuit portion and facing the edge coupler; and
a dummy chip disposed next to the glass connector on the optical integrated circuit portion, the dummy chip having an upper surface on a same plane as a vertical level of an uppermost surface of the logic chip structure, a vertical level of an uppermost surface of the first memory chip structure, and a vertical level of an uppermost surface of the second memory chip structure.
Claim 20 is allowable by virtue of dependency from claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nie et al. (US 2023/0090133 A1) discloses an integrated circuit die (130) edge coupled to a waveguide (140) in a glass layer (110), thereby teachings a glass connector (110/140) mounted adjacent an integrated circuit die (130) and edge coupled with a port (132) of the integrated circuit die (130);
Eisherbini et al. (US 2024/0061194 A1) discloses a package substrate (118), an interposer (102-1), and a photonics chip structure (102-2/102-3; see Figure 1A, 1B) comprising an electronic integrated circuit portion (102-2) including an electronic integrated circuit chip (EIC) mounted on an interposer (102-1) and an optical integrated circuit portion (102-3) including an optical integrated circuit chip (104) with an active surface including a waveguide (160) that is coupled to a fiber connector (187) located in a groove on the bottom corner of the photonics chip structure (102-2/102-3; see Figure 1A), and an alternative embodiment including groove (portion containing optical component 183 in Figure 2) on a bottom corner of the photonics chip structure (102-2/102-3) with an optical coupler (183) in the groove between the waveguide (160) and the fiber (187);
Wu et al. (US 2023/0369274 A1) discloses an integrated circuit package (see the entire disclosure; in particular Figures 25A and 25B regarding the optical connection assembly); and
Hsia et al. (US 2024/0107781 A1) discloses an integrated circuit package (see the entire disclosure).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE R CONNELLY whose telephone number is (571)272-2345. The examiner can normally be reached Monday-Friday, 9 AM to 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874
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