Notice of Pre-AIA or AIA St
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on January 15, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 15, 2026 has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2022/0343842) in view of Chang et al (US 2019/0088208).
As per claim 1 Yu discloses: A display substrate, comprising:
a base substrate; and a plurality of sub-pixels on the base substrate, wherein the plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns {[0043] Specifically, the pixel driving circuit is applied to a display device, and the display device includes a substrate, a plurality of pixel driving circuits arranged on the substrate in an array, and a plurality of light-emitting elements EL arranged on a side of the plurality of pixel driving circuits away from the substrate and corresponding to the plurality of pixel driving circuits in a one-to-one manner.}, each sub-pixel comprises a light-emitting element EL and a pixel circuit for driving the light-emitting element EL to emit light, and the light-emitting element EL is configured to emit light according to a driving current that is received {[0051] Voled is the operating voltage of the light-emitting element EL, and the driving current I generated when the driving sub-circuit 1 connects its first terminal and the second terminal};
the pixel circuit comprises a driving circuit 1, a data writing circuit 5, a storage circuit 22, and a light-emitting control circuit 8 {figure 5};
the driving circuit 1 comprises a control end, a first end {figure 6: gate of T3}, and a second end, and is configured to control the driving current flowing through the light-emitting element EL, the first end of the driving circuit 1 receives a first voltage of a first voltage line {figure 6: one electrode T3 is connect to VDD via T5}, and the second end of the driving circuit 1 is connected to the light-emitting control circuit 8 {figure 6: the other electrode of T3 is connected to circuit 8};
the data writing circuit 5 is connected to the control end of the driving circuit 1 {figure 6: connection is via Cst1}, and is configured to write a data signal into the control end of the driving circuit 1 in response to a first scan signal { [0047] In the threshold compensation period P2, as shown in FIG. 7 and FIG. 9, under the control of the reset signal inputted by the reset signal line RE, the first reset sub-circuit 61 controls to disconnect the first power line VDD from the control terminal of the driving sub-circuit 1; the initialization signal line Init inputs the initialization voltage Vinit, and under the control of the first scan signal inputted by the first gate line GA1, the first control sub-circuit 71 controls to connect the initialization signal line Init and the second terminal of the driving sub-circuit 1 (i.e., the N3 node), so that the potential of the second terminal of the driving sub-circuit 1 become Vinit; at the same time, under the control of the first scan signal inputted by the first gate line GA1, the compensation sub-circuit 4 controls to connect the control terminal of the driving sub-circuit 1 and the first terminal of the driving sub-circuit 1.};
a first end of the light-emitting control circuit 8 is connected to the second end of the driving circuit 1, a second end of the light-emitting control circuit 8 is connected to a first electrode of the light-emitting element EL, and the light-emitting control circuit 8 is configured to apply the driving current to the light-emitting element EL in response to a light-emitting control signal {figures 5-6};
a first end of the storage circuit 22 is connected to the control end of the driving circuit 1, a second end of the storage circuit 22 is connected to the second end of the light-emitting control circuit 8, and the storage circuit 22 is configured to store the data signal written by the data writing circuit 5 {figures 5-6}; and
Regarding claim 1 Yu is silent as to: orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of the plurality of sub-pixels on the base substrate are mirror-symmetrical. With respect to claim 1 Chang et al discloses: orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of the plurality of sub-pixels on the base substrate are mirror-symmetrical { [0045] In configurations for display 14 with mirror symmetry pixel layouts and pairs of data lines of the type shown in FIGS. 7 and 8, the space consumed by signal lines can be reduced by consolidating signal lines such as the power supply lines and reference voltage lines.}
It would have been obvious to a person having ordinary skill in the art at the time the invention was effectively filed to provide the display substrate of Yu with orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of the plurality of sub-pixels on the base substrate are mirror-symmetrical as taught by Chang et al. The rationale is as follows: one of ordinary skill in the art at the time the invention was effectively filed would have been motivated to provide a display substrate with orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of the plurality of sub-pixels on the base substrate are mirror-symmetrical so that the wiring can be shared by the neighboring pixels thereby simplifying the wiring of the display.
Allowable Subject Matter
Claims 2-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The primary reason for the indication of allowable subject matter, with respect to claim 2, is the inclusion of:
The display substrate according to claim 1, wherein the plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit at least comprises three adjacent sub- pixels located in a same row, and each pixel unit comprises a first sub-pixel, a second sub- pixel, and a third sub-pixel arranged in sequence along a first direction; a data writing circuit in a pixel circuit of the first sub-pixel is connected to a first data line to receive a corresponding data signal; a data writing circuit in a pixel circuit of the second sub-pixel is connected to a second data line to receive a corresponding data signal; a data writing circuit in a pixel circuit of the third sub-pixel is connected to a third data line to receive a corresponding data signal; the first data line, the second data line, and the third data line extend in a second direction, and the second direction is perpendicular to the first direction, wherein the first data line is on a side of the first sub-pixel away from the second sub- pixel, and the second data line and the third data line are between the second sub-pixel and the third sub-pixel; or the first data line and the second data line are between the first sub-pixel and the second sub-pixel, and the third data line is on a side of the third sub-pixel away from the second sub-pixel.
The prior art does not show the claimed arrangement of sub-pixels and data lines best depicted in figure 3.
The primary reason for the indication of allowable subject matter, with respect to claims 3-20, is the inclusion of:
The display substrate according to claim 1, wherein the first voltage line comprises a first voltage main line and a first voltage bridging line, the first voltage main line extends along a second direction, the first voltage bridging line extends along a first direction, the first voltage bridging line is connected to the first voltage main line through a first hole, and the first voltage bridging line is configured to provide the first voltage to two rows of the plurality of sub- pixels respectively on two sides of the first voltage bridging line and adjacent to the first voltage bridging line.
The prior art does not show the claimed arrangement of the bridging line, main line and hole best depicted in figure 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID D DAVIS whose telephone number is (571)272-7572. The examiner can normally be reached Monday - Friday, 8 a.m. - 4 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID D DAVIS/Primary Examiner, Art Unit 2627
DDD
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