DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/10/2026 has been entered.
Response to Amendment
1. Amendments filed on 05/27/2026 have been entered. Claims 1, 16, and 18 have been amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
2. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Feng et al (US 2025/0014662).
As to claim 1, Feng teaches a gate driver comprising a plurality of signal transmission units cascade-connected to one another and configured to receive a clock signal and sequentially output gate signals, wherein at least one of the plurality of signal transmission units includes:
a first circuit unit (the first display input circuit 7 and the first display reset circuit 8, Fig. 19) configured to control charging or discharging of a Q node (as illustrated in fig. 19, and the corresponding waveform of fig. 17, the first display input circuit 7, charges the first pull-up node PU1, and the first display reset circuit 8, discharges the first pull-up node PU1);
a second circuit unit including an inverter circuit (M13, Fig. 19) configured to invert the potential of the Q node and apply the inverted potential to a Qb node (when the first pull-up node PU1 is connected to the high voltage level VDD1, M13 will be turned no to transmit the low voltage level VGL1 to the first pull-down node PD1, Fig. 19); and
a third circuit unit including:
a first pull-up transistor (M16, Fig. 19) connected to be turned on based on a potential of the Q node (PU1, fig. 19);
a second pull-up transistor (M15, Fig. 19) connected to be turned on based on the potential of the Q node (PU1, fig. 19);
a first pull-down transistor (M19, fig. 19) connected to be turned on based on a potential of the Qb node (PD1, fig. 19);
a second pull-down transistor (M18, fig. 19) connected to be turned on based on the potential of the Qb node (PD1, fig. 19); and
an Ath transistor (M71, Fig. 19) disposed between the first pull-up transistor (M16, Fig. 19) and the second pull-up transistor (M15, Fig. 19) and configured to electrically separate the Q node (PU1, fig. 19) from the second pull- up transistor (M15, Fig. 19) in response to a control signal independently of a signal at the Q node or any signal that controls the signal at the Q node (a switch signal input terminal SW, fig. 19).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2025/0014662) in view of Lai et al (US 2022/0076618).
As to claim 2, Feng teaches the gate driver, wherein the at least one of the plurality of signal transmission units further includes a Bth transistor (M3, Fig. 19) disposed between the first pull-up transistor (M16, Fig. 19) and the second pull-up transistor (M15, Fig. 19) and configured to supply (VDD1, Fig. 19) to the second pull-up transistor in response to a control bar signal (CLKA, Fig. 19).
Feng does not teach supplying a second low potential voltage as claimed.
However, Lai teaches a Bth transistor (M2, fig. 5) configured to supply a second low potential voltage (VG11,[0035] the other one of the third voltage signal VG11 or the fourth voltage signal VG22 is a low level signal) to the second pull-up transistor (M5, fig. 5) in response to a control bar signal (CRL, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng to teach a Bth transistor configured to supply a second low potential voltage the second pull-up transistor in response to a control bar signal as suggested by Lai. The motivation would have been in order to “satisfy different voltage requirements of the pixel circuit for different signals” ([0004]).
As to claim 3, Feng in view of Lai teaches the gate driver, wherein the Bth transistor (Feng: M3, Fig. 19) is disposed between the Ath transistor (Feng: M71, Fig. 19) and the second pull-up transistor (Feng: M15, Fig. 19).
4. Claim(s) 4 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2025/0014662) in view of Lai et al (US 2022/0076618) and further in view of Miyake et al (US 2010/0201659).
As to claim 4, Feng in view of Lai teach the gate driver, further comprising: a first output terminal (Feng: a first cascade output circuit 13, Fig. 19) configured to output a carry signal (Feng: CR, Fig. 19) in response to operations of the first pull-up transistor (Feng: M16, Fig. 19) and the first pull-down transistor (Feng: M19, fig. 19); a second output terminal (Feng: a second driving output circuit 9, Fig. 19) configured to output the gate signal (Feng: out1, Fig. 19) in response to operations of the second pull-up transistor (Feng: M15, Fig. 19) and the second pull-down transistor (Feng: M18, fig. 19);
Feng in view of Lai do not teach a Cth transistor as claimed.
However, Miyake teaches a Cth transistor (121, fig. 1D) connected to the second output terminal (Gout, fig. 1D) to supply a first low potential voltage (VSS, fig. 1D) in response to the control bar signal (CKB, fig. 1D).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng and Lai to teach a Cth transistor connected to the second output terminal to supply a first low potential voltage in response to the control bar signal as suggested by Miyake. The motivation would have been in order to suppress degradation of characteristics in transistors ([0005]).
As to claim 16, Feng teaches a gate driver comprising an nth signal transmission unit and an (n+1)th signal transmission unit configured to receive a clock signal and sequentially output gate signals and cascade-connected to each other, n being a positive integer of 1 or more, wherein each of the nth signal transmission unit and the (n+1)th signal transmission unit includes:
a first circuit unit (the first display input circuit 7 and the first display reset circuit 8, Fig. 19) configured to control charging or discharging of a Q node (as illustrated in fig. 19, and the corresponding waveform of fig. 17, the first display input circuit 7, charges the first pull-up node PU1, and the first display reset circuit 8, discharges the first pull-up node PU1);
a second circuit unit including an inverter circuit (M13, Fig. 19) configured to invert the potential of the Q node and apply the inverted potential to a Qb node (when the first pull-up node PU1 is connected to the high voltage level VDD1, M13 will be turned no to transmit the low voltage level VGL1 to the first pull-down node PD1, Fig. 19);
a first output terminal (a first cascade output circuit 13, Fig. 19) configured to output a carry signal (CR, Fig. 19) in response to operations of the first pull-up transistor (M16, Fig. 19) and the first pull-down transistor (M19, fig. 19);
a second output terminal (a second driving output circuit 9, Fig. 19) configured to output the gate signal (out1, Fig. 19) in response to operations of the second pull-up transistor (M15, Fig. 19) and the second pull-down transistor (M18, fig. 19);
a third circuit unit including:
a first pull-up transistor (M16, Fig. 19) connected to be turned on based on a potential of the Q node (PU1, fig. 19);
a second pull-up transistor (M15, Fig. 19) connected to be turned on based on the potential of the Q node (PU1, fig. 19);
a first pull-down transistor (M19, fig. 19) connected to be turned on based on a potential of the Qb node (PD1, fig. 19);
a second pull-down transistor (M18, fig. 19) connected to be turned on based on the potential of the Qb node (PD1, fig. 19);
an Ath transistor (M71, Fig. 19) disposed between the first pull-up transistor (M16, Fig. 19) and the second pull-up transistor (M15, Fig. 19) and configured to electrically separate the Q node (PU1, fig. 19) from the second pull- up transistor in response to a control signal independently of a signal at the Q node or any signal that controls the signal at the Q node (a switch signal input terminal SW, fig. 19);
a Bth transistor (M3, Fig. 19) disposed between the Ath transistor (M71, Fig. 19) and the second pull-up transistor (M15, Fig. 19) and configured to supply (VDD1, Fig. 19) to the second pull-up transistor in response to a control bar signal (CLKA, Fig. 19); and
Feng does not teach supplying a second low potential voltage as claimed.
However, Lai teaches a Bth transistor (M2, fig. 5) configured to supply a second low potential voltage (VG11,[0035] the other one of the third voltage signal VG11 or the fourth voltage signal VG22 is a low level signal) to the second pull-up transistor (M5, fig. 5) in response to a control bar signal (CRL, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng to teach a Bth transistor configured to supply a second low potential voltage the second pull-up transistor in response to a control bar signal as suggested by Lai. The motivation would have been in order to “satisfy different voltage requirements of the pixel circuit for different signals” ([0004]).
Feng in view of Lai do not teach a Cth transistor as claimed.
However, Miyake teaches a Cth transistor (121, fig. 1D) connected to the second output terminal (Gout, fig. 1D) to supply a first low potential voltage (VSS, fig. 1D) in response to the control bar signal (CKB, fig. 1D).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng and Lai to teach a Cth transistor connected to the second output terminal to supply a first low potential voltage in response to the control bar signal as suggested by Miyake. The motivation would have been in order to suppress degradation of characteristics in transistors ([0005]).
5. Claim(s) 5-8, 13-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2025/0014662) in view of Lai et al (US 2022/0076618) and further in view of Miyake et al (US 2010/0201659) and further in view of Lee et al (US 2021/0407427).
As to claim 5, Feng in view of Lai and further in view of Miyake do not teach the gate driver as claimed.
However, Lee teaches the gate driver, wherein the control bar signal is a gate-off voltage when the control signal is a gate-on voltage, and the control bar signal is a gate-on voltage when the control signal is a gate-off voltage (Fig. 12 shows when MS1 is high, MS1B is low and vice versa).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng in view of Lai and further in view of Miyake to teach, the gate driver, as suggested by Lee. The motivation would have been in order to reduce a power consumption ([0007]).
As to claim 6, Feng in view of Lai, and further in view of Miyake and further in view of Lee teach the gate driver, wherein a gate electrode of the Ath transistor (Feng: M71, Fig. 19) is connected to a control signal input terminal configured to receive the control signal (Feng: SW, Fig. 19), a first electrode of the Ath transistor is connected to the Q node (Feng: the first pull-up node PU1), and a second electrode of the Ath transistor is connected to a gate electrode of the second pull-up transistor (Feng: M15, Fig. 19).
As to claim 7, Feng teaches the gate driver, wherein a gate electrode of the Bth transistor (M3, Fig. 19) is connected to a first control bar signal input terminal configured to receive the control bar signal (CLKA, Fig. 19), a first electrode of the Bth transistor is connected to receive (VDD1, Fig. 19), and a second electrode of the Bth transistor is connected to a gate electrode of the second pull-up transistor (M15, Fig. 19).
Feng does not teach a first electrode of the Bth transistor is connected to receive the second low potential voltage as claimed.
However, Lai teaches a first electrode of the Bth transistor (M2, fig. 5) is connected to receive the second low potential voltage (VG11, [0035] the other one of the third voltage signal VG11 or the fourth voltage signal VG22 is a low-level signal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng to teach a Bth transistor as suggested by Lai. The motivation would have been in order to “satisfy different voltage requirements of the pixel circuit for different signals” ([0004]).
As to claim 8, Feng in view of Lai, and further in view of Miyake and further in view of Lee teach the gate driver, wherein a gate electrode of the Cth transistor (Miyake: 121, fig. 1D) is connected to a second control bar signal input terminal configured to receive the control bar signal (Miyake: CKB, fig. 1D), a first electrode of the Cth transistor is connected to receive the first low potential voltage (Miyake: VSS, fig. 1D), and a second electrode of the Cth transistor is connected to the second output terminal (Miyake: Gout, fig. 1D).
As to claim 13, Feng in view of Lai, and further in view of Miyake and further in view of Lee teach the gate driver, wherein, when the control signal is changed from a gate-on voltage to a gate-off voltage, the control bar signal is changed from a gate-off voltage to a gate-on voltage (Lee: Fig. 12 shows when MS1 is high, MS1B is low and vice versa).
As to claim 14, Feng in view of Lai, and further in view of Miyake and further in view of Lee teach the gate driver, wherein, when the control signal is changed from a gate-on voltage to a gate-off voltage, an ON-OFF relationship between the first pull-up transistor and the second pull-up transistor is inverted (Lee: Fig. 12 shows when MS1 becomes high, MT22 will be turned off and MT23 is turned off as the result).
As to claim 15, Feng in view of Lai, and further in view of Miyake and further in view of Lee teach the gate driver, wherein, when the control signal is changed from a gate-on voltage to a gate-off voltage, a gate signal is changed from a gate-on voltage to a gate-off voltage (Lee: Fig. 12 shows when MS1 changes from high to low, GI1 changes from low to high).
As to claim 17, Feng in view of Lai and further in view of Miyake do not teach the gate driver as claimed.
However, Lee teaches the gate driver, wherein, when a gate signal output from the (n+1)th signal transmission unit is changed from a gate-off voltage to a gate-on voltage, a gate signal output from the nth signal transmission unit is changed from the gate-on voltage to the gate-off voltage (Lee: see GI1 and GI2 in fig. 12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng in view of Lai and further in view of Miyake to teach, the gate driver, as suggested by Lee. The motivation would have been in order to reduce a power consumption ([0007]).
6. Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0082328) in view of Feng et al (US 2025/0014662).
As to claim 18, Feng328 teaches a display device comprising:
a gate driver including an nth signal transmission unit (a first stage of shift register unit A1, Fig. 9) and an (n+1)th signal transmission unit (second stage of shift register unit A2, fig. 9) that are cascade-connected to each other, n being a positive integer of 1 or more (fig. 9 illustrates that the first stage of shift register unit A1 and the second stage of shift register unit A2 are cascadly connected to each other );
an nth pixel line set including an nth odd-numbered pixel line that receives an nth gate signal output from the nth signal transmission unit and an nth even-numbered pixel line that receives the nth gate signal output from the nth signal transmission unit ([0109] The first scan signal output terminals OUT1 and the second scan signal terminals OUT2 of the respective stages of shift register units of the gate driving circuit 20 may be configured to be sequentially connected to the plurality of rows of gate lines for outputting the driving signals. Note that fig. 10 illustrates that OUT1<1> and OUT2<1> from the first stage of shift register unit A1 (see fig. 9) for two adjacent pixel lines are the same signals and generated at the same time, [0111]); and
an (n+1)th pixel line set including an (n+1)th odd-numbered pixel line that receives an (n+1)th gate signal output from the (n+1)th signal transmission unit and an (n+1)th even- numbered pixel line that receives an (n+1)th gate signal output from the (n+1)th signal transmission unit ([0109] The first scan signal output terminals OUT1 and the second scan signal terminals OUT2 of the respective stages of shift register units of the gate driving circuit 20 may be configured to be sequentially connected to the plurality of rows of gate lines for outputting the driving signals. Note that fig. 10 illustrates that OUT1<2> and OUT2<2> from the second stage of shift register unit A2 (see fig. 9) for two adjacent pixel lines are the same signals and generated at the same time, [0111]),
wherein, for a sensing time for external compensation, when the nth gate signal is a gate- on voltage, the (n+1)th gate signal is a gate-off voltage, and when the (n+1)th gate signal is a gate-on voltage, the nth gate signal is a gate-off voltage ([0127] the signals output from the scan signal output terminals (the first scan signal output terminal OUT1 <1> and the second scan signal output terminal OUT2 <1>) can be used to drive sense transistors in the sub-pixel units in the display panel to achieve external compensation, [0137] during the blanking period of each frame, the gate driving circuit outputs driving signals for sense transistors in sub-pixel units in a display panel, and the driving signals are sequentially provided row by row. For example, in the blanking period of the first frame, the gate driving circuit outputs a driving signal for sub-pixel units in a first row of the display panel, in the blanking period of the second frame, the gate driving circuit outputs a driving signal for sub-pixel units in a second row of the display panel, and so on, so as to complete the sequential progressive compensation), and
wherein at least one of the nth signal transmission unit or the (n+1)th signal transmission unit includes:
a first circuit unit (M5 and M6 together, Fig. 1) configured to control charging or discharging a Q node (as illustrated in fig. 1, a fifth transistor M5 charges the pull-up node Q with VDD; the sixth transistor M6 discharges the pull-up node Q with VGL1);
a second circuit unit including an inverter circuit (eighth transistor M8, Fig. 1) configured to invert the potential of the Q node and apply the inverted potential to a Qb node (when the potential of Q node becomes VDD, M8 may be turned on to discharge the QB node with VGL1, Fig. 1); and3
a third circuit unit including:
a first pull-up transistor (M11, Fig. 1) connected to be turned on based on a potential of the Q node (Q node, Fig. 1),
a second pull-up transistor (M15, Fig. 1) connected to be turned on based on the potential of the Q node (Q node, Fig. 1),
a first pull-down transistor (M12, Fig. 1) connected to be turned on based on a potential of the Qb node (QB, Fig. 1),
a second pull-down transistor (M16, Fig. 1) connected to be turned on based on the potential of the Qb node (QB, Fig. 1); and
Feng328 does not teach an Ath transistor as claimed.
However, Feng662 teaches an Ath transistor (M71, Fig. 19) disposed between the first pull-up transistor (M16, Fig. 19) and the second pull-up transistor (M15, Fig. 19) and configured to electrically separate the Q node (PU1, fig. 19) from the second pull- up transistor (M15, Fig. 19) in response to a control signal independently of a signal at the Q node or any signal that controls the signal at the Q node (a switch signal input terminal SW, fig. 19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng328 to add, an Ath transistor, as suggested by Feng662. The motivation would have been in order to provide a sensing control anti-leakage circuit to improve the performance of a shift register ([0013]).
At to claim 19, Feng328 in view of Feng662 teach the display device, wherein, for the sensing time for external compensation, when the nth gate signal is a gate-off voltage, the (n+1)th gate signal is a gate-on voltage, and when the (n+1)th gate signal is a gate-off voltage, the nth gate signal is a gate-on voltage (Feng328: [0127] the signals output from the scan signal output terminals (the first scan signal output terminal OUT1 <1> and the second scan signal output terminal OUT2 <1>) can be used to drive sense transistors in the sub-pixel units in the display panel to achieve external compensation, [0137] during the blanking period of each frame, the gate driving circuit outputs driving signals for sense transistors in sub-pixel units in a display panel, and the driving signals are sequentially provided row by row. For example, in the blanking period of the first frame, the gate driving circuit outputs a driving signal for sub-pixel units in a first row of the display panel, in the blanking period of the second frame, the gate driving circuit outputs a driving signal for sub-pixel units in a second row of the display panel, and so on, so as to complete the sequential progressive compensation).
At to claim 20, Feng328 teaches a pixel circuit included in the nth pixel line set and the (n+1)th pixel line set (Feng: [0127] ).
Feng328 does not teach a pixel circuit as claimed.
However, Feng662 teaches the display device, wherein each pixel circuit (see figure 1) includes a third switch element (STFT, Fig. 1) including a gate electrode configured to receive the nth gate signal or the (n+1)th gate signal (G2, Fig. 1), a first electrode connected to a fourth node connected to an anode of a light emitting element (OLED, Fig. 1), and a second electrode configured to receive a sensing voltage (Sense line, Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng328 to add, a pixel circuit, as suggested by Feng662. The motivation would have been in order to provide a sensing control anti-leakage circuit to improve the performance of a shift register ([0013]).
Allowable Subject Matter
7. Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMEN W BOGALE/ Examiner, Art Unit 2628
/NITIN PATEL/ Supervisory Patent Examiner, Art Unit 2628
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