DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Amendments filed on 09/04/2025 have been entered. Claims 1, 16, and 18 have been amended.
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1, 16, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 2021/0407427).
As to claim 1, Lee teaches a gate driver comprising a plurality of signal transmission units cascade-connected to one another (ST1-STn+4, fig. 5) and configured to receive a clock signal (CLK1 and CLK2, fig. 5) and sequentially output gate signals ([0108], fig. 5),
wherein at least one of the plurality of signal transmission units includes:
a first pull-up transistor (NT9, fig. 11) connected to be turned on based on a potential of a Q node (N3, fig. 11);
a second pull-up transistor (MT23, fig. 11) connected to be turned on based on the potential of the Q node (N3, fig. 11);
a first pull-down transistor (NT10, fig. 11) connected to be turned on based on a potential of a Qb node (N2, fig. 11);
a second pull-down transistor (MT24, fig. 11) connected to be turned on based on the potential of the Qb node (N2, fig. 11); and
an Ath transistor (MT22, fig. 11) disposed between the first pull-up transistor and the second pull-up transistor and configured to electrically separate the Q node (N3, fig. 11) from the second pull-up transistor (MT23, fig. 11) in response to a control signal independently of a signal at the Q node or any signal that controls the signal at the Q node (a first masking signal MS1, fig. 11).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2021/0407427) in view of Lai et al (US 2022/0076618).
As to claim 2, Lee teaches the gate driver, wherein the at least one of the plurality of signal transmission units further includes a Bth transistor (MT21, fig. 11) disposed between the first pull-up transistor (NT9, fig. 11) and the second pull-up transistor (MT23, fig. 11) and configured to supply voltage (VGH, fig. 11) to the second pull-up transistor in response to a control bar signal (MS1B, fig. 11).
Lee does not teach supplying a second low potential voltage as claimed.
However, Lai teaches a Bth transistor (M2, fig. 5) configured to supply a second low potential voltage (VG11,[0035] the other one of the third voltage signal VG11 or the fourth voltage signal VG22 is a low level signal) to the second pull-up transistor (M5, fig. 5) in response to a control bar signal (CRL, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee to teach a Bth transistor configured to supply a second low potential voltage the second pull-up transistor in response to a control bar signal as suggested by Lai. The motivation would have been in order to “satisfy different voltage requirements of the pixel circuit for different signals” ([0004]).
As to claim 3, Lee in view of Lai teaches the gate driver, wherein the Bth transistor (Lee: MT21, fig. 11) is disposed between the Ath transistor (Lee: MT22, fig. 11) and the second pull-up transistor (Lee: MT23, fig. 11).
5. Claim(s) 4-8 and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2021/0407427) in view of Lai et al (US 2022/0076618) and further in view of Miyake et al (US 2010/0201659).
As to claim 4, Lee in view of Lai teaches the gate driver, further comprising: a first output terminal configured to output a carry signal (Lee: GCj-4, fig. 11) in response to operations of the first pull-up transistor (Lee: NT9, fig. 11) and the first pull-down transistor (Lee: NT10, fig. 11); a second output terminal configured to output the gate signal (Lee: GIj, fig. 11) in response to operations of the second pull-up transistor (Lee: MT23, fig. 11) and the second pull-down transistor (Lee: MT24, fig. 11);
Lee in view of Lai does not teach a Cth transistor as claimed.
However, Miyake teaches a Cth transistor (121, fig. 1D) connected to the second output terminal (Gout, fig. 1D) to supply a first low potential voltage (VSS, fig. 1D) in response to the control bar signal (CKB, fig. 1D).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee and Lai to teach a Cth transistor connected to the second output terminal to supply a first low potential voltage in response to the control bar signal as suggested by Miyake. The motivation would have been in order to suppress degradation of characteristics in transistors ([0005]).
As to claim 5, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein the control bar signal is a gate-off voltage when the control signal is a gate-on voltage, and the control bar signal is a gate-on voltage when the control signal is a gate-off voltage (Lee: Fig. 12 shows when MS1 is high, MS1B is low and vice versa).
As to claim 6, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein a gate electrode of the Ath transistor (Lee: MT22, fig. 11) is connected to a control signal input terminal configured to receive the control signal (Lee: MS1, fig. 11), a first electrode of the Ath transistor is connected to the Q node (Lee: N3, fig. 11), and a second electrode of the Ath transistor is connected to a gate electrode of the second pull-up transistor (Lee: MT23, fig. 11).
As to claim 7, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein a gate electrode of the Bth transistor (Lee: MT21, fig. 11) is connected to a first control bar signal input terminal configured to receive the control bar signal (Lee: MS1B, fig. 11), a first electrode of the Bth transistor is connected to receive the (Lee: VGH, fig. 11), and a second electrode of the Bth transistor is connected to a gate electrode of the second pull-up transistor (Lee: MT23, fig. 11 ).
Lee does not teach a first electrode of the Bth transistor is connected to receive the second low potential voltage as claimed.
However, Lai teaches a first electrode of the Bth transistor (M2, fig. 5) is connected to receive the second low potential voltage (VG11, [0035] the other one of the third voltage signal VG11 or the fourth voltage signal VG22 is a low-level signal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee to teach a Bth transistor as suggested by Lai. The motivation would have been in order to “satisfy different voltage requirements of the pixel circuit for different signals” ([0004]).
As to claim 8, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein a gate electrode of the Cth transistor (Miyake: 121, fig. 1D) is connected to a second control bar signal input terminal configured to receive the control bar signal (Miyake: CKB, fig. 1D), a first electrode of the Cth transistor is connected to receive the first low potential voltage (Miyake: VSS, fig. 1D), and a second electrode of the Cth transistor is connected to the second output terminal (Miyake: Gout, fig. 1D).
As to claim 13, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein, when the control signal is changed from a gate-on voltage to a gate-off voltage, the control bar signal is changed from a gate-off voltage to a gate-on voltage (Lee: Fig. 12 shows when MS1 is high, MS1B is low and vice versa).
As to claim 14, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein, when the control signal is changed from a gate-on voltage to a gate-off voltage, an ON-OFF relationship between the first pull-up transistor and the second pull-up transistor is inverted (Lee: Fig. 12 shows when MS1 becomes high, MT22 will be turned off and MT23 is turned off as the result).
As to claim 15, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein, when the control signal is changed from a gate-on voltage to a gate-off voltage, a gate signal is changed from a gate-on voltage to a gate-off voltage (Lee: Fig. 12 shows when MS1 changes from high to low, GI1 changes from low to high).
As to claim 16, Lee teaches a gate driver comprising an nth signal transmission unit and an (n+1)th signal transmission unit (ST1-STn+4, fig. 5) configured to receive a clock signal (CLK1 and CLK2, fig. 5) and sequentially output gate signals and cascade-connected to each other ([0108], fig. 5), n being a positive integer of 1 or more,
wherein each of the nth signal transmission unit and the (n+1)th signal transmission unit includes:
a first pull-up transistor (NT9, fig. 11) configured to be turned on based on a potential of a Q node (N3, fig. 11);
a second pull-up transistor (MT23, fig. 11) configured to be turned on based on the potential of the Q node (N3, fig. 11);
a first pull-down transistor (NT10, fig. 11) configured to be turned on based on a potential of a Qb node (N2, fig. 11);
a second pull-down transistor (MT24, fig. 11) configured to be turned on based on the potential of the Qb node (N2, fig. 11);
a first output terminal configured to output a carry signal (GCj-4, fig. 11) in response to operations of the first pull-up transistor and the first pull-down transistor (NT9 and NT10, fig. 11);
a second output terminal configured to output the gate signal (GIj, fig. 11) in response to operations of the second pull-up transistor and the second pull-down transistor (MT23 and MT24, fig. 11); an
Ath transistor (MT22, fig. 11) disposed between the first pull-up transistor and the second pull- up transistor and configured to electrically separate the Q node (N3, fig. 11) from the second pull-up transistor (MT23, fig. 11) in response to a control signal independently of a signal at the Q node or any signal that controls the signal at the Q node (a first masking signal MS1, fig. 11);
a Bth transistor (MT21, fig. 11) disposed between the Ath transistor (MT22, fig. 11) and the second pull-up transistor (MT23, fig. 11) and configured to supply (VGH, fig. 11) to the second pull-up transistor in response to a control bar signal (MS1B, fig. 11).
Lee does not teach supplying a second low potential voltage as claimed.
However, Lai teaches a Bth transistor (M2, fig. 5) configured to supply a second low potential voltage (VG11,[0035] the other one of the third voltage signal VG11 or the fourth voltage signal VG22 is a low level signal) to the second pull-up transistor (M5, fig. 5) in response to a control bar signal (CRL, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee to teach a Bth transistor configured to supply a second low potential voltage the second pull-up transistor in response to a control bar signal as suggested by Lai. The motivation would have been in order to “satisfy different voltage requirements of the pixel circuit for different signals” ([0004]).
Lee in view of Lai does not teach a Cth transistor as claimed.
However, Miyake teaches a Cth transistor (121, fig. 1D) connected to the second output terminal (Gout, fig. 1D) to supply a first low potential voltage (VSS, fig. 1D) in response to the control bar signal (CKB, fig. 1D).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee and Lai to teach a Cth transistor connected to the second output terminal to supply a first low potential voltage in response to the control bar signal as suggested by Miyake. The motivation would have been in order to suppress degradation of characteristics in transistors ([0005]).
As to claim 17, Lee in view of Lai and further in view of Miyake teaches the gate driver, wherein, when a gate signal output from the (n+1)th signal transmission unit is changed from a gate-off voltage to a gate-on voltage, a gate signal output from the nth signal transmission unit is changed from the gate-on voltage to the gate-off voltage (Lee: see GI1 and GI2 in fig. 12).
6. Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0082328) in view of Lee et al (US 2021/0407427).
As to claim 18, Feng teaches a display device comprising:
a gate driver including an nth signal transmission unit (a first stage of shift register unit A1, Fig. 9) and an (n+1)th signal transmission unit (second stage of shift register unit A2, fig. 9) that are cascade-connected to each other, n being a positive integer of 1 or more (fig. 9 illustrates that the first stage of shift register unit A1 and the second stage of shift register unit A2 are cascadly connected to each other );
an nth pixel line set including an nth odd-numbered pixel line that receives an nth gate signal output from the nth signal transmission unit and an nth even-numbered pixel line that receives the nth gate signal output from the nth signal transmission unit ([0109] The first scan signal output terminals OUT1 and the second scan signal terminals OUT2 of the respective stages of shift register units of the gate driving circuit 20 may be configured to be sequentially connected to the plurality of rows of gate lines for outputting the driving signals. Note that fig. 10 illustrates that OUT1<1> and OUT2<1> from the first stage of shift register unit A1 (see fig. 9) for two adjacent pixel lines are the same signals and generated at the same time, [0111]); and
an (n+1)th pixel line set including an (n+1)th odd-numbered pixel line that receives an (n+1)th gate signal output from the (n+1)th signal transmission unit and an (n+1)th even- numbered pixel line that receives an (n+1)th gate signal output from the (n+1)th signal transmission unit ([0109] The first scan signal output terminals OUT1 and the second scan signal terminals OUT2 of the respective stages of shift register units of the gate driving circuit 20 may be configured to be sequentially connected to the plurality of rows of gate lines for outputting the driving signals. Note that fig. 10 illustrates that OUT1<2> and OUT2<2> from the second stage of shift register unit A2 (see fig. 9) for two adjacent pixel lines are the same signals and generated at the same time, [0111]),
wherein, for a sensing time for external compensation, when the nth gate signal is a gate- on voltage, the (n+1)th gate signal is a gate-off voltage, and when the (n+1)th gate signal is a gate-on voltage, the nth gate signal is a gate-off voltage ([0127] the signals output from the scan signal output terminals (the first scan signal output terminal OUT1 <1> and the second scan signal output terminal OUT2 <1>) can be used to drive sense transistors in the sub-pixel units in the display panel to achieve external compensation, [0137] during the blanking period of each frame, the gate driving circuit outputs driving signals for sense transistors in sub-pixel units in a display panel, and the driving signals are sequentially provided row by row. For example, in the blanking period of the first frame, the gate driving circuit outputs a driving signal for sub-pixel units in a first row of the display panel, in the blanking period of the second frame, the gate driving circuit outputs a driving signal for sub-pixel units in a second row of the display panel, and so on, so as to complete the sequential progressive compensation), and
wherein at least one of the nth signal transmission unit or the (n+1)th signal transmission unit includes:
a first pull-up transistor (M13, fig. 1) connected to be turned on based on a potential of a Q node (Q, fig. 1);
a second pull-up transistor (M15, fig. 1) connected to be turned on based on the potential of the Q node (Q, fig. 1); and
Feng does not teach the Ath transistor as claimed.
However, Lee teaches an Ath transistor (MT22, fig. 11) disposed between the first pull-up transistor (NT9, fig. 11) and the second pull- up transistor (MT23, fig. 11) and configured to electrically separate the Q node (N3, fig. 11) from the second pull-up transistor (MT23, fig. 11) in response to a control signal (MS1, fig. 11) independently of a signal at the Q node or any signal that controls the signal at the Q node (a first masking signal MS1, fig. 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng to teach, an Ath transistor, as suggested by Lee. The motivation would have been in order to provide “a driving circuit capable of reducing the power consumption” ([0008]).
At to claim 19, Feng in view of Lee teaches the display device, wherein, for the sensing time for external compensation, when the nth gate signal is a gate-off voltage, the (n+1)th gate signal is a gate-on voltage, and when the (n+1)th gate signal is a gate-off voltage, the nth gate signal is a gate-on voltage (Feng: [0127] the signals output from the scan signal output terminals (the first scan signal output terminal OUT1 <1> and the second scan signal output terminal OUT2 <1>) can be used to drive sense transistors in the sub-pixel units in the display panel to achieve external compensation, [0137] during the blanking period of each frame, the gate driving circuit outputs driving signals for sense transistors in sub-pixel units in a display panel, and the driving signals are sequentially provided row by row. For example, in the blanking period of the first frame, the gate driving circuit outputs a driving signal for sub-pixel units in a first row of the display panel, in the blanking period of the second frame, the gate driving circuit outputs a driving signal for sub-pixel units in a second row of the display panel, and so on, so as to complete the sequential progressive compensation),
7. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0082328) in view of Lee et al (US 2021/0407427) and further in view of Kim et al (US 2022/0180815).
As to claim 20, Feng in view of Lee teaches pixel circuit included in the nth pixel line set and the (n+1)th pixel line set (Feng: [0127] )
Feng in view of Lee does not teach a third pixel element as claimed.
However, Kim teaches the display device, wherein each pixel circuit (Fig. 2B) included in the nth pixel line set and the (n+1)th pixel line set includes a third switch element (SENT, fig. 2B) including a gate electrode configured to receive the nth gate signal or the (n+1)th gate signal (SENSE, fig. 2B), a first electrode connected to a fourth node connected to an anode of a light emitting element (ED, fig. 2B), and a second electrode configured to receive a sensing voltage (Vref, fig. 2B)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Feng in view of Lee to teach, a pixel circuit, as suggested by Kim. The motivation would have been in order to compensate pixels in a high temperature condition and prevent image degradation (abstract).
Allowable Subject Matter
8. Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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