DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakahara (US 2005/0068705).
In regard to Claim 1:
Nakahara discloses, in Figure 3, a self-protection circuitry, configured to receive a first power source (1), and comprising:
a first transistor circuit (7), comprising a first input terminal (7 drain), a first output terminal (7 source), and a first control terminal (7 gate), wherein the first output terminal is electrically connected to a ground terminal (7 source is electrically connected to 2), and the first input terminal is configured to receive the first power source (7 drain is electrically connected to 1);
a first switch circuit (12), electrically connected to the first control terminal (7 gate) and the first input terminal (7 and 12 are electrically connected together via 1); and
a control circuit (11), electrically connected to the first switch circuit (12), and configured to: before the first power source (1) supplies power to the first transistor circuit (7), control the first switch circuit (12) to be conducted (¶ 0033), and after the first power source (1) continuously supplies power to the first transistor circuit (7), control the first switch circuit to be cut off (¶ 0034).
In regard to Claim 2:
Nakahara discloses, in Figure 3, the self-protection circuitry according to claim 1, wherein the control circuit controls, before the first power source stops supplying power to the first transistor circuit, the first switch circuit to be conducted.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Laraia (US 6,882,513).
In regard to Claim 10:
Laria discloses, in Figure 4, an operational amplifier circuit, configured to receive a first power source (401), and comprising:
a current mirror circuit (20/5 and 160/5);
a first transistor circuit (431), comprising a first input terminal (431 source), a first output terminal (431 drain), and a first control terminal (431 gate), wherein the first input terminal (431 source) and the first control terminal (431 gate) are electrically connected to the current mirror circuit (20/5, 160/5), the first input terminal is configured to receive the first power source (431 is connected to 401), and the first output terminal is electrically connected to a ground terminal (431 is connected to 412);
a first switch circuit (450), electrically connected to the first input terminal (431 source and 450 source are connected together via 401) and the first control terminal (431 gate connected to 450 drain); and
a control circuit (482), electrically connected to the first switch circuit (450), and configured to: before the first power source (401) supplies power to the first transistor circuit (431), control the first switch circuit (450) to be conducted (Column 5: lines 23-42, Column 7: lines 44-45), and after the first power source (401) continuously supplies power to the first transistor circuit (431), control the first switch circuit (450) to be cut off (Column 5: lines 23-42, Column 7: lines 44-45).
In regard to Claim 11:
Nakahara discloses, in Figure 3, the operational amplifier circuit according to claim 10, wherein the control circuit (482) controls, before the first power source (401) stops supplying power to the first transistor circuit (431), the first switch circuit (450) to be conducted (Column 8: lines 3-25).
Allowable Subject Matter
Claims 3-6 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 3:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a third switch circuit, electrically connected between the first power source and the first input terminal, wherein the control circuit is electrically connected to the second switch circuit and the third switch circuit, to control the second switch circuit and the third switch circuit to be separately conducted or cut off.
However, Nakahara (US 2005/0068705) discloses, in Figure 3, a second switch circuit (6), electrically connected between the first control terminal (7 gate) and the ground terminal (2).
In regard to Claim 12:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a second transistor circuit, comprising a second input terminal, a second control terminal, and a second output terminal, wherein the second control terminal is electrically connected to the second input terminal, the second input terminal is configured to receive the second power source, and the second output terminal is electrically connected to the ground terminal; a third transistor circuit, comprising a third input terminal, a third control terminal, and a third output terminal, wherein the second control terminal is electrically connected to the third control terminal, the third input terminal is configured to receive the second power source, and the third output terminal is electrically connected to the ground terminal; and a second switch circuit, electrically connected to the third control terminal and the third input terminal, wherein the control circuit is electrically connected to the second switch circuit, and is configured to: before the second power source supplies power to the current mirror circuit, control the second switch circuit to be conducted, and after the second power source continuously supplies power to the current mirror circuit, control the second switch circuit to be cut off.
Claims 7-9 are allowed.
In regard to Claim 7:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a second transistor circuit, comprising a second input terminal, a second output terminal, and a second control terminal, wherein the first output terminal is electrically connected to the second input terminal, and the second output terminal is electrically connected to a ground terminal; a second switch circuit, electrically connected to the second control terminal and the second input terminal; and a control circuit, electrically connected to the first switch circuit and the second switch circuit, and configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit and the second switch circuit to be conducted, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit and the second switch circuit to be cut off.
However, Nakahara (US 2005/0068705) discloses, in Figure 3, a first transistor circuit (7), comprising a first input terminal (7 drain), a first output terminal (7 source), and a first control terminal (7 gate), wherein the first output terminal is electrically connected to a ground terminal (7 source is electrically connected to 2), and the first input terminal is configured to receive the first power source (7 drain is electrically connected to 1); a first switch circuit (12), electrically connected to the first control terminal (7 gate) and the first input terminal (7 and 12 are electrically connected together via 1); and a control circuit (11) configured to: before the first power source (1) supplies power to the first transistor circuit (7), control the first switch circuit (12) to be conducted (¶ 0033), and after the first power source (1) continuously supplies power to the first transistor circuit (7), control the first switch circuit to be cut off (¶ 0034).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tobita (US 7,317,441) discloses a first amplifier circuit (132) included in a voltage generating circuit (114) includes a differential circuit formed of P-type TFT elements (P101, P102) and N-type TFT elements (N101, N102), a constant current circuit (150a, 150b) and an N-type TFT element (N103). Constant current circuit (150a; 150b) includes a P-type TFT element (P132a; P132b), a capacitor (C132a; C132b), switches (S104a-S106a; S104b-S106b) and a resistance element (R132a; R132b). Capacitor (C132a; C132b) holds a voltage on a node (204; 208) in a voltage setting operation, and thus when a current is being supplied to the diode-connected P-type TFT element (P132a; P132b).
Nakahara (US 2009/0147422) discloses a power supply control circuit (300) has an output transistor (109) which is provided between an output terminal (106) and a positive terminal of battery power supply (101). An electrical path is formed between the positive terminal of the battery power supply and a control terminal of the output transistor to set a switch transistor (114) conductive, when the power supply is reversely connected. The electrical path is disconnected, when the power supply is normally connected.
Chen et al. (US 2016/0372918) discloses an electrostatic discharge (ESD) protection control circuit for an output pad of an integrated circuit includes an output driver and a control switch. The output driver, coupled to the output pad, includes a first output transistor for outputting power or signals to the output pad. The control switch, for improving ESD protection on the output pad when closed, includes a first connection terminal, coupled to a gate terminal of the first output transistor; a second connection terminal, coupled to a ground terminal; and a control terminal, coupled to a first power supply terminal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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