Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is objected to because:
The Cross-Reference to Related Applications section in paragraph [0001] of the specification does not provide the status of U.S. application serial no. 18/918,743 (i.e., now U.S. Patent No. 12,142,335).
Drawings
The formal drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 8-14 of U.S. Patent No: 12,142,335.
For example, claim 10 of the present application teaches “A method by a memory system, comprising: writing data to a first address of the memory system and a first set of parity bits to a second address of the memory system, wherein the first set of parity bits is based at least in part on the data and the first address; reading the data from the first address and the first set of parity bits from the second address based at least in part on receiving a read command that indicates the first address; generating a second set of parity bits using the data read from the first address and the first address indicated by the read command; and performing one or more error detection or error correction operations on the data, the first address the data is read from, or any combination thereof, to determine a source of an error based at least in part on determining that the data, the first address the data is read from, or any combination thereof are associated with an error”. Whereas claim 8 of U.S. PN: 12,142,335 teaches “A method, comprising: receiving, at a memory device from a host device via a command/address bus, a command for accessing memory of the memory device, the command comprising an address of the memory from which to read data; reading the data and a first set of parity bits from the memory, wherein the data is read from a first portion of the memory corresponding to the address and the first set of parity bits is read from a second portion of the memory different than the first portion; generating, at the memory device using an error control code, a second set of parity bits based at least in part on reading the data and the first set of parity bits from the memory, wherein the second set of parity bits is generated using the address of the memory received and the data read from the first portion of the memory; and determining at least one error associated with the data read from the memory, the address received, the address of the memory the data is read from, or any combination thereof based at least in part on the first set of parity bits and the second set of parity bits”.
The examiner would like to emphasize that although the two inventions are not “exactly” the same, they are obvious variations of each other and not patentably distinct because one is just an embodiment of the other and also the process remains the same.
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim 1 of the instant application and claim 8 of U.S. Patent No. 12,142,335 are generally directed to different statutory embodiments of the same invention. That is, claim 1 of the instant application is directed to a machine, while claim 8 of U.S. Patent No. 12,142,335 is directed to a method. Although the conflicting claims are not identical, they are not patentably distinct from each other because claim 1 of the instant application is the machine version of the method limitations cited in claim 8 of U.S. Patent No. 12,142,335. Therefore, the claims are obvious variations of each other and not patentably distinct.
Claim 19 of the instant application and claim 8 of U.S. Patent No. 12,142,335 are generally directed to different statutory embodiments of the same invention. That is, claim 1 of the instant application is directed to a computer–readable medium, while claim 8 of U.S. Patent No. 12,142,335 is directed to a method. Although the conflicting claims are not identical, they are not patentably distinct from each other because claim 1 of the instant application is a computer–readable medium version of the method limitations cited in claim 8 of U.S. Patent No. 12,142,335. Therefore, the claims are obvious variations of each other and not patentably distinct.
Dependent claims 2-7, 9-18 and 20 of the instant application are deemed obvious over the dependent claims 9-14 of the U.S. Patent No. 12,142,335 for the same rationales discussed above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9-13, and 18-20 are rejected under 35 U.S.C. 102(a) (2) as being anticipated by Kaushik et al. “Kaushik” (US: 2023/0153197).
Regarding claim 1, Kaushik substantially teaches a memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system (see figure 1 and par. [003] and [0032] to write data to a first address of the memory system and a first set of parity bits to a second address of the memory system, wherein the first set of parity bits is based at least in part on the data and the first address; read the data from the first address and the first set of parity bits from the second address based at least in part on receiving a read command that indicates the first address (see par. [0031], [0038]-[0040]; generate a second set of parity bits using the data read from the first address and the first address indicated by the read command; and perform one or more error detection or error correction operations on the data, the first address the data is read from, or any combination thereof, to determine a source of an error based at least in part on determining that the data, the first address the data is read from, or any combination thereof are associated with an error (see par. [0031], [0041] - [0040]).
Regarding Claim 2, Kaushik substantially discloses the claimed invention as indicated in claim 1 including wherein the processing circuitry is further configured to cause the memory system to: read the data from the first address and the first set of parity bits from the second address based at least in part on receiving a second read command that indicates the first address; generate a third set of parity bits using the data read from the first address and the first address indicated by the second read command; determine whether the data, the first address the data is read from, the first address indicated by the second read command, or any combination thereof is associated with an error based at least in part on the first set of parity bits and the third set of parity bits and transmit signaling to a host device that indicates the data read from the first address based at least in part on determining that the data, the first address the data is read from, or any combination thereof is not associated with an error (see paragraphs [0003-0004], [0031], [0040] - [0041], and [0073]).
Regarding Claim 3, Kaushik substantially discloses the claimed invention as indicated in claim 1 including wherein the processing circuitry is further configured to cause the memory system to: transmit signaling to a host device that indicates that the first set of parity bits and the second set of parity bits do not match based at least in part on determining that the data, the first address the data is read from, or any combination thereof is associated with an error (see paragraphs [0003-[004] and [0073]).
Regarding Claim 4, Kaushik substantially discloses the claimed invention as indicated in claim 1 including wherein determining whether the data, the first address the data is read from, or any combination thereof is associated with an error comprises the processing circuitry configured to cause the memory system to: compare, by an error control component of the memory system, the first set of parity bits and the second set of parity bits (see paragraphs [0003]-[004] and [0077]).
Regarding Claims 9 and 18, Kaushik substantially discloses wherein the processing circuitry is further configured to cause the memory system to: decode the first address of the memory system into a row address and a column address based at least in part on receiving a command to write the data to the first address, wherein the row address and the column address comprise respective sets of bits that are different than a set of bits associated with the first address the data is written to (see figure 2 and paragraph [0058]).
Claim 10, and 19, these claims are directed to a method and computer readable medium and are rejected for the same reasons as in claim 1.
Claim 11, and 20, these claims are directed to a method and computer readable medium and are rejected for the same reasons as in claim 2.
Claim 12, this claim is directed to a method and is rejected for the same reasons as in claim 3.
Claim 13, this claim is directed to a method and is rejected for the same reasons as in claim 4.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-8 and 14-17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kaushik et al. “Kaushik” (US: 2023/0153197) in view of Li (U.S. PN: 11,169.881).
As per clams 5 and 14:
Kaushik substantially teaches the claimed invention described in claim 1 (as indicated above).
However, Kaushik does not explicitly teach a first set of intermediate parity bits using the first address that the data is written to; and generate, during a second operation different than the first operation, a second set of intermediate parity bits using the data.
Li, in an analogous art, teaches teach a first set of intermediate parity bits using the first address that the data is written to; and generate, during a second operation different than the first operation, a second set of intermediate parity bits using the data. (see col. 2, lines 24-36).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kaushik with the teachings of Li by generating a first set of intermediate parity bits using the first address that the data is written to; and generate, during a second operation different than the first operation, a second set of intermediate parity bits using the data.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized by generating a first set of intermediate parity bits using the first address that the data is written to; and generate, during a second operation different than the first operation, a second set of intermediate parity bits using the data would have improved security and performance of the system.
As per claims 6 and 15:
The combination of Kaushik and Li in the above rejection teach wherein the processing circuitry is further configured to cause the memory system to: generate, during a third operation, the first set of parity bits based at least in part on the first set of intermediate parity bits and the second set of intermediate parity bits (see col. 2, lines 24-36 in Li).
As per claims 7 and 16:
The combination of Kaushik and Li in the above rejection teach wherein the first address the data is written to is in a first portion of memory of the memory system and the second address is in a second portion of the memory that is different than the first portion of the memory, and the processing circuitry is further configured to cause the memory system to: rout the first set of intermediate parity bits to a first bank of memory of a plurality of banks of memory based at least in part on generating the first set of intermediate parity bits, wherein the first bank of memory includes the first portion of the memory and the second portion of the memory, and wherein generating the first set of parity bits is based at least in part on routing the first set of intermediate parity bits to the first bank of memory of the plurality of banks of memory (see col. 2, lines 52-64 and col. 11, lines 38-52 in Li).
As per claims 8 and 17:
The combination of Kaushik and Li in the above rejection teach wherein the first set of intermediate parity bits comprises a first quantity of bits and the first address the data is written to comprises a second quantity of bits greater than the first quantity of bits (see col. 8, lines 41-67 to col. 9, lines 1-38 in Li).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US-11392454) describe a memory module includes a plurality of data chips configured to store a user data set and meta data, a first parity chip and a second parity chip configured to store a first parity data and a second parity data, respectively, the first parity data and the parity data being generated based on the user data set and the meta data, and a buffer chip configured to provide the user data set and the meta data to the plurality of data chips based on a command and an address provided from an external memory controller and configured to provide the first parity data and the second parity data to the first parity chip and the second parity chip, respectively. The buffer chip includes an error correction code (ECC) engine circuitry, a memory management circuitry configured to control the ECC engine, and an error managing circuitry.
Adham et al. (U.S. PN: 11,379,298) teach a memory circuit includes: a single-port memory interface which includes a sole address port configured to receive a read/write (RW) address, and a multi-port memory which has multiple address ports coupled to the sole address port of the single-port memory interface, and which is configured to store a data unit and parity bits, some of the parity bits being based on the corresponding RW address; a first decoding circuit configured to generate a decoded write address from the RW address and the parity bits; and an error detecting circuit configured to determine if an address error exists based on a comparison of the decoded write address to the read address.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112