DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakahara (US 2009/0128973).
In regard to Claim 1:
Nakahara discloses, in Figure 7, a self-protection circuitry, configured to receive a first power source, and comprising:
a first transistor circuit (109), comprising a first input terminal (109 drain), a first output terminal (109 source), and a first control terminal (109 gate), wherein the first input terminal is configured to receive the first power source (109 drain connected to 101; ¶ 0085), and the first output terminal is electrically connected to a ground terminal (109 source connected to 102 via 112; ¶ 0085);
a first switch circuit (108), electrically connected to the first input terminal (109 drain via 107, 110, 111) and the ground terminal (102 via 112); and
a control circuit (105), electrically connected to the first switch circuit (108), and configured to: before the first power source (1010 supplies power to the first transistor circuit (109), control the first switch circuit (108) to be turned on (¶ 0095), and after the first power source (101) continuously supplies power to the first transistor circuit (109), control the first switch circuit (108) to be turned off (¶ 0092).
In regard to Claim 2:
Nakahara discloses, in Figure 7, the self-protection circuitry according to claim 1, wherein the control circuit (105) controls, before the first power source (101) stops supplying power to the first transistor circuit (109), the first switch circuit to be turned on (¶ 0095).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakahara (US 2009/0128973), in view of Laraia (US 6,882,513).
In regard to Claim 10:
Nakahara discloses, in Figure 7, an operational amplifier circuit, configured to receive a first power source, and comprising: a first transistor circuit (109), comprising a first input terminal (109 drain), a first output terminal (109 source), and a first control terminal (109 gate), wherein the first input terminal is configured to receive the first power source (109 drain connected to 101; ¶ 0085), and the first output terminal is electrically connected to a ground terminal (109 source connected to 102 via 112; ¶ 0085); a first switch circuit (108), electrically connected to the first input terminal (109 drain via 107, 110, 111) and the ground terminal (102 via 112); and a control circuit (105), electrically connected to the first switch circuit (108), and configured to: before the first power source (1010 supplies power to the first transistor circuit (109), control the first switch circuit (108) to be turned on (¶ 0095), and after the first power source (101) continuously supplies power to the first transistor circuit (109), control the first switch circuit (108) to be turned off (¶ 0092).
Nakahara does not disclose a current mirror circuit, wherein the first input terminal and the first control terminal are electrically connected to the current mirror circuit.
Laraia discloses, in Figure 4, a current mirror circuit (25/3, 25/5), wherein the first input terminal (450 source) and the first control terminal (450 gate) are electrically connected to the current mirror circuit (both 450 source and 450 gate are connected to 25/5 of the 25/3 and 25/5 current mirror).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the current mirror taught by Laraia with the control circuit taught by Nakahara, in order to have a smaller design that does not require complex circuitry and reduce the voltage drop across the protection circuit when normal supply voltages are applied (Laraia Column 2: lines 47-52).
In regard to Claim 11:
Nakahara further discloses, in Figure 7, the operational amplifier circuit according to claim 10, wherein the control circuit (105) controls, before the first power source (101) stops supplying power to the first transistor circuit (109), the first switch circuit to be turned on (¶ 0095).
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 3:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a third switch circuit, electrically connected between the first power source and the first input terminal, wherein the control circuit is electrically connected to the second switch circuit and the third switch circuit, to control the second switch circuit and the third switch circuit to be separately turned on or turned off.
However, Nakahara discloses, in Figure 7, a second switch circuit (115), electrically connected between the first control terminal (109 gate via 113, 116) and the ground terminal (102); and a third switch circuit (110).
Claims 7-9 are allowed.
In regard to Claim 7:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
a second transistor circuit, comprising a second input terminal, a second output terminal, and a second control terminal, wherein the first output terminal is electrically connected to the second input terminal, and the second output terminal is electrically connected to a ground terminal; a second switch circuit, electrically connected to the second control terminal and the second input terminal; and a control circuit, electrically connected to the first switch circuit and the second switch circuit, and configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit and the second switch circuit to be turned on, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit and the second switch circuit to be turned off.
Nakahara discloses, in Figure 7, a first transistor circuit (109), comprising a first input terminal (109 drain), a first output terminal (109 source), and a first control terminal (109 gate), wherein the first input terminal is configured to receive the first power source (109 drain connected to 101; ¶ 0085), and
a first switch circuit (108), electrically connected to the first input terminal (109 drain via 107, 110, 111) and the ground terminal (102 via 112).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakahara (US 2009/0147422) discloses a power supply control circuit includes a control circuit that controls an output transistor to be rendered conductive by forming a second electrical path between a second power supply line and a control terminal of the output transistor when a power supply voltage is applied in a reverse direction between first and second power supply lines, and that controls a second electrical path to be electrically disconnected when the power supply voltage is applied in a forward direction between the first and second power supply lines.
Wang et al. (US 2010/0123985) discloses Various apparatuses, methods and systems for protecting a driver from electrostatic discharge. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.
Fan (US 10,903,807) discloses a transconductance stage circuit, a switch stage circuit and a load stage circuit which are electrically connected in sequence. The transconductance stage circuit is used to access a radio frequency voltage signal and convert the radio frequency voltage signal into a radio frequency current signal The switch-level circuit is used to access the local oscillator signal and the radio frequency current signal, and the switch-level transistor is turned on by using the local oscillator signal; the load-level circuit is used to convert the intermediate frequency current signal into a voltage signal for output. In the present invention, the transconductance stage circuit adopts a transistor superposition technology structure, which improves the conversion gain of the mixer; at the same time, it uses a source degenerate inductance structure, which further improves the conversion gain and linearity of the circuit.
Nakahara (US 2005/0068705) discloses a surge voltage detecting unit (11) monitors the voltage of a first power supply (1), and turns ON a MOS transistor (12) when the voltage of the first power supply increases to a voltage higher than a predetermined voltage. The control switch is connected between the first power supply and a dynamic clamping circuit (10).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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