DETAILED ACTION
This office action is in response to application 18/918,894 filed 10/17/2024 that claims priority to provisional application 63/605,951 filed 12/04/2023.
Claims 1-20 have been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Gupta (Gupta US 2013/0297865 A1).
Regarding claim 1, Gupta teaches A method, comprising: (Gupta [0008] teaches the inventive concepts are directed to a method for processing commands and addresses associated with access requests.)
providing a first access command, for a first address of a target memory device, (Gupta [0008] discloses there may be a first address and first command associated with a first port to a DRAM device (a target memory device).) to a first bin of the target memory device, (Per para [0039] of the instant application a bin is a virtual area of the target device. Gupta [0048] discloses the addresses may be a virtual address and each port of the DRAM 1100 is associated with a different set of addresses. Thus Gupta identifies each port with a set of logical addresses that represent one or more bins.) wherein the target memory device includes a plurality of ports (Gupta [0008] discloses there may be a second command to a second port, thus the device includes a plurality of ports.) and the first access command is provided to the first bin utilizing a first port from the plurality of ports; (Gupta [0008] and [0048] discloses a first command with a first address is provided to the first port associated with a first set of logical addresses (a first bin).)
and providing a second access command, for a second address of the target memory device, to a second bin of the target memory device, (Gupta [0008] and [0048] discloses a second command with a second address is provided to the second port associated with a second set of logical addresses (a second bin).)
wherein the second address has a first offset from the first address, (Consistent with para [0051] of the instant application, a second address may have an offset from a first address when they differ by an amount. See the example from para [0051] shows a first address of 31 and a second address of 32 means the second address has an offset from the first address of 1. Gupta [0008] discloses there may be a first address and a second address, there is a difference (offset) between the first address and the second address as they represent different locations of the memory. Thus the second address has an offset from the first address.)
wherein the second access command is provided to the second bin utilizing a second port from the plurality of ports, (Gupta [0008] and [0048] discloses a second command with a second address is provided to a second port associated with a second set of addresses (a second bin).)
and wherein the first access command and the second access command are provided by an initiator device to the first bin and the second bin (Consistent with para [0034] of the instant application, an initiator may be any device that can provide commands to the memory device and/or receive data from the memory device. Gupta Fig. 1 and para [0025] discloses the access requests come from controller 105 within a Device 102, thus the device 102 is an example of an initiator. ) via an interconnect that connects the initiator device to the target memory device. (Gupta Fig. 1 and para [0025] discloses memory interface 100 that connects the Device 102 (the initiator) to the target memory device (Multi-Port DRAM 110.)
Regarding claim 2, Gupta teaches the limitations of claim 1 above. Gupta further teaches wherein, responsive to the second address being offset from the first address, providing the second access command utilizing the second port (Gupta [0048] discloses that each port in the Muti-Port DRAM 110 that contains 2 ports has a set of logical addresses associated with it. Thus the Controller 105 will send a second command that is not within the range of the first port, and thus at an offset outside of the first ports range, to the second port. See also Gupta Fig. 2C and [0039]-[0042] providing a second command for the second port.)
Regarding claim 3, Gupta teaches the limitations of claim 1 above. Gupta further teaches further comprising: receiving first data responsive to providing the first access command; and receiving second data responsive to providing the second access command. (Gupta Fig. 2B and [0034]-[0038] and [0048]-[0050] discloses the system transmits the command, address, and data information to their respective ports. Thus the first data is sent to the memory and received by the memory responsive to receiving a first access command, and the second data is sent to and received at the memory responsive to receiving a second access command. Examiner notes the ‘first data’ may be the command, address, and data information associated with the command request.)
Regarding claim 4, Gupta teaches the limitations of claim 3 above. Gupta further teaches further comprising performing a first plurality of operations utilizing the first data and a second plurality of operations utilizing the second data. (Gupta Fig. 2 B and [0034]-[0038] and [0048]-[0050] discloses that transferring the first and second commands and data to the first and second ports comprises a plurality of operations such as implement a CLK, setting up the CMD/ADDR bus, and placing data on the DQ-PO and DQ-P1 lines according to the clock cycle. Thus the system performs a plurality of operations for the each command (i.e. each data).)
Regarding claim 5, Gupta teaches the limitations of claim 4 above. Gupta further teaches further comprising: providing a third access command, for a third address of the target memory device, to the first bin of the target memory device responsive to performing the first plurality of operations, wherein the third access command is provided to the first bin utilizing the first port from the plurality of ports; (Gupta [0048] discloses that each port may have a per-port ordering of read and write commands. Thus there may be two requests to the set of addresses for the first port, and the system will perform a second request following the first request to the first port (i.e. responsive to performing the first plurality of operations that is the first request to the first port of the plurality of 4 requests).)
and providing a fourth access command, for a fourth address of the target memory device, to the second bin of the target memory device responsive to performing the second plurality of operations, wherein the fourth access command is provided to the second bin utilizing the second port from the plurality of ports. (Gupta [0048] discloses that each port may have a per-port ordering of read and write commands. Thus there may be two requests to the set of addresses for the second port, and the system will perform a second request to the second port following the first request to the second port (i.e. responsive to performing the second plurality of operations that is the first request to the second port of the plurality of the 4 requests).)
Regarding claim 6, Gupta teaches the limitations of claim 5 above. Gupta further teaches wherein the third address has a second offset from the first address. (Gupta [0048] discloses that each port in the Muti-Port DRMA 110 that contains 2 ports has a set of logical addresses associated with it. Gupta further discloses there may be a plurality of per-port read and write commands. Thus there may be a first command with a first address to the first port, and a second command with a second address to the first port. There will be an offset between the two requests that is the difference between the first and second address. Thus the third address has a second offset from the first address to the first request to the first port.)
Regarding claim 7, Gupta teaches all of the limitations of claim 6 above. Gupta further teaches wherein the fourth address has the second offset from the second address. (Gupta [0012] teaches a binary search that divides the memory in half (identifying the midpoints) enable simultaneous access to the memory to more quickly locate a data element. Thus Gupta in would search a first address to a first memory in a first port, followed by a first address to a second memory, followed by a second address to a second memory in a first port, followed by a second address to a second memory, etc. as shown below:
PNG
media_image1.png
433
775
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Greyscale
Note that in the above scenario the offsets would be as follows:
1st offset (1st to 2nd access address) = 2m
2nd offset (1st to 3rd access address) = ½ m
3rd offset (2nd to 4th access address) = ½ m
4th offset (3rd to 4th access address ) = 2m
Thus the third offset between the second and fourth address is a second offset value of ½ m (which is also the value of the second offset between the 1st and 3rd access requests whose value is also 1/2m), and thus teaches ‘wherein the fourth address has the second offset from the second address’.
Regarding claim 8, Gupta teaches all of the limitations of claim 6 above. Gupta further teaches wherein the fourth address has the first offset from the third address. (Gupta [0012] teaches a binary search that divides the memory in half (identifying the midpoints) enable simultaneous access to the memory to more quickly locate a data element. Thus Gupta in would search a first address to a first memory in a first port, followed by a first address to a second memory, followed by a second address to a second memory in a first port, followed by a second address to a second memory, etc. as shown above. Gupta teaches a 4th offset that is an offset of 2m between the 3rd access and the 4th access.)
Claims 9-12 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamaraj (Kamaraj et al., US 2022/0206707 A1)
Regarding claim 9, Kamaraj teaches An apparatus, comprising: (Kamaraj Fig. 1 and para [0016] that discloses a host that may be a laptop computer and a Memory Sub-system that may be a device that is connected by a physical ) a target device that includes a plurality of ports; (Gupta [0056] discloses memory storage divided into two portions, each portion accessed by a separate port.) an initiator device coupled to the target device (Consistent with para [0034] of the instant application, an initiator may be any device that can provide commands to the memory device and/or receive data from the memory device. Kamaraj [0023] discloses controller 115 receives commands from the host and converts the commands to instructions or commands to achieve the desired memory access to the memory devices. Kamaraj [0021] discloses controller 155 may be a device. Thus the controller 155 is an example of an initiator devices that sends commands to the memory device or receives data from the memory device.)
and configured to: perform a plurality of searches (Kamaraj [Abstract] discloses the memory banks are split into a plurality of slots. Kamaraj [0012] discloses memory sub-system performs a parallel search of the slots to quickly locate data in the memory system. See also Kamaraj [claim 4] that discloses the memory banks (composed of slots divided into rows) are searched in parallel.)
utilizing a plurality of bins of the target device (Kamaraj [Abstract] discloses the memory device is a logical array composed of a plurality of memory banks to store data. See also Kamaraj Fig. 3 and para [0040-[0050] discloses the logical array may be composed of a plurality of memory banks 341-1 to 341-3, thus there may be a plurality of banks and each bank contains a subset of the logical array, thus contains one or more bins.) and the plurality of ports; (Kamaraj [00042] discloses each memory bank is accessed using a data port and an address port. Thus the logical array subsections that comprise a memory bank of Fig.3 are accessed utilizing a plurality of ports.)
wherein a first search from the plurality of searches is a binary search (Kamaraj [0010] discloses a convention means of searching is a binary search, thus the first search may be a binary search) and utilizes a first port from the plurality of ports (Kamaraj [00042] discloses each memory bank is accessed using a data port and an address port.) and a first bin from the plurality of bins; (Kamaraj [Abstract], Fig. 3 para [0040-[0050] discloses the logical array may be composed of a plurality of memory banks 341-1 to 341-3, where each bank is a subset of the logical array, and memory associated with memory bank 341-1 may be a first bin.)
and wherein a second search from the plurality of searches begins at a second address that is offset from the first address and utilizes a second port from the plurality of ports and a second bin from the plurality of bins. (Kamaraj [0020], Fig. 3 and [0040]-[0050], most notably [0042] and [0045] discloses there may be a second search of Bank 341-2 using a second address port. Note also that the three memory banks of Fig. 3 are of the same size and would have a same midpoint value (i.e. the same relative value, thus the second address is offset from the first address based on the number of addresses within each memory bank, thus the second midpoint is an offset from the first address and utilizes a second address port of the plurality of ports.)
Regarding claim 10, Kamaraj teaches all of the limitations of claim 9 above. Kamaraj further discloses wherein each search of the plurality of searches utilizes a different bin, that is different, from the plurality of bins. (Kamaraj Fig. 3 and [0040]-[0050] discloses the searches performed in parallel per Kamaraj [0012] would search the Memory Banks 341-1 and 341-2 in parallel and are directed to different logical memory locations. See also Kamaraj [0042] that each separate memory bank uses a separate address port to connect its (logical) elements to the rows of its memory bank (it’s separate bin).)
Regarding claim 11, Kamaraj teaches all of the limitations of claim 9 above. Kamaraj further teaches wherein the initiator device configured to perform the plurality of searches is further configured to provide a plurality of access commands to the plurality of bins, wherein the plurality of access commands is provided in a first iteration of the plurality of searches. (Kamaraj [0023] discloses the memory subsystem 115 converts the commands received from the host into command instructions to access the memory devices. Thus when Kamaraj [0012] discloses searching the memory banks in parallel it will generate a plurality of access commands in parallel (where the first iteration is the first search performed at each bank).)
Regarding claim 12, Kamaraj teaches all of the limitations of claim 11 above. Kamaraj further teaches wherein the initiator device is further configured to provide each access command from the plurality of access commands utilizing a different port from the plurality of ports. (Kamaraj [0012] discloses the components of the memory sub-system can perform a parallel search of the slots to quickly locate data in the memory system. Kamaraj [0023] discloses controller 115 receives commands from the host and converts the commands to instructions or commands to achieve the desired memory access to the memory devices. Kamaraj Fig. 3 and para [0040-[0050] discloses the logical array may be composed of a plurality of memory banks 341-1 to 341-3. Kamaraj [00042] discloses each memory bank is accessed using a data port and an address port for the bank. Thus each search request is sent to the plurality of banks 341-1 through 341-3 through three sets of address/data ports, one set per memory bank and thus is providing the access commands that are the plurality of access commands to perform the searching utilizing a different port for each memory bank (thus utilizing a different port from the plurality of ports).)
Regarding claim 17, Kamaraj teaches An apparatus, comprising: a target device that includes a first plurality of ports and a second plurality of ports; (Kamaraj Figs. 1 and 3 and paras [0013], [0028], [0040]-[0050] discloses memory subsystem that is a device (thus an apparatus) contains a logical array may be composed of a plurality of memory banks 341-1 to 341-3. Kamaraj [0028] and [0042] discloses each memory bank is associated with a data port and an address port. Thus the target contains a first plurality of ports on 341-1 and a second plurality of ports on 341-2.)
an initiator device coupled to the target device (Consistent with para [0034] of the instant application, an initiator may be any device that can provide commands to the memory device and/or receive data from the memory device. Kamaraj [0023] discloses controller 115 receives commands from the host and converts the commands to instructions or commands to achieve the desired memory access to the memory devices. Kamaraj [0021] discloses controller 155 may be a device. Thus the controller 155 is an example of an initiator devices that sends commands to the memory device or receives data from the memory device.)
and configured to: perform a first search (Kamaraj [0012] and [claim 4] discloses the components of the memory sub-system can perform a parallel search of the banks to quickly locate data in the memory system. See also Kamaraj Fig. 3 and [0040]-[0050] that discloses there may be a plurality of banks, including 341-1 that may perform a first search) utilizing a first bin of the target device (Kamaraj [Abstract] and Fig. 3 paras [0040]-[0050] discloses the logical array may be composed of a plurality of memory banks 341-1 to 341-3, where each bank contains a subset of the logical array and its memory dedicated to 341-1 is an example of a first bin of the target device.) and the first plurality of ports; (Kamaraj [0028] and [0042] discloses each memory bank is associated with a data port and an address port. Thus the first bank that performs a first search does so using a first plurality of ports).
perform a second searches (Kamaraj [0012] and [claim 4] discloses the components of the memory sub-system can perform a parallel search of the banks to quickly locate data in the memory system. See also Kamaraj Fig. 3 and [0040]-[0050] that discloses there may be a plurality of banks, including 341-2 that may perform a second search) utilizing a second bin of the target device (Kamaraj [Abstract] and Fig. 3 paras [0040]-[0050] discloses the logical array may be composed of a plurality of memory banks 341-1 to 341-3, where each bank contains a subset of the logical array and its memory dedicated to 341-2 is an example of a second bin of the target device.) and the second plurality of ports; (Kamaraj [0028] and [0042] discloses each memory bank is associated with a data port and an address port. Thus the second bank that performs a second search does so using a second plurality of ports).
wherein a first iteration of the first search begins at a first plurality of addresses (Kamaraj [0010] discloses the parallel searches may be a binary search by repeatedly dividing the list in half. Kamaraj [0045] discloses that the search begins at a first midpoint. Thus Kamaraj [0010] and [0045] discloses if the data is not found at the first midpoint, the system will search a second midpoint between the first midpoint and the first or last memory locations per the binary search process. Kamaraj [0042] discloses that the data within each memory bank is accessed using an address port. Thus the midpoint location that is accessed using a first address. Thus the first midpoint is a first address and the second midpoint is a second address and the first search begins at a first plurality of addresses) and utilizes the first plurality of ports and the first bin from a plurality of bins of the target device; (Kamaraj Fig. 3 and [Abstract] [0028] [0042] [0040]-[0050] discloses the search to first bank 341-1 is performed using a first set of address and data ports of 341-1 and the memory associated with bank 341-1 (first bin for Memory Bank 341-1). )
and wherein a first iteration of the second search begins at a second plurality of addresses (Kamaraj Fig. 3 and [Abstract] [0028] [0042] [0040]-[0050] discloses the system may search a second bank 341-2 at a first midpoint (a first address) and a second midpoint (a second address) is performed using a first set of address and data ports of 341-2 and the memory associated with bank 341-2 (second bin for Memory Bank 341-2). )and utilizes the second plurality of ports and the second bin from the plurality of bins. (Kamaraj Fig. 3 and [Abstract] [0028] [0042] [0040]-[0050] discloses the search to second bank 341-2 is performed using data ports of 341-2 and second set of memory (second bin for Memory Bank 341-2.). )
Regarding claim 18, Kamaraj teaches the limitations of claim 17 above. Kamaraj further teaches wherein the first plurality of addresses has a first offset from the second plurality of addresses. (Consistent with para [0051] of the instant application, a second address may have an offset form a first address when they differ by an amount. Kamaraj Fig. 3 and [0012], [0020], and [0040]-[0050], most notably [0042], [0045] discloses there may be a first search that starts at the midpoint of Bank 341-1 and may include a second midpoint within 341-1 and a second search that starts at the midpoint of Bank 341-2 and includes a second midpoint within 341-2. Note also that the three memory banks of Fig. 3 are of the same size and would have a same midpoint value (i.e. the same relative value). Thus the midpoint of 341-2 is offset from the midpoint of 341-1 and thus the first plurality of address has a first offset (its first midpoint) from the midpoint of the second plurality of addresses.)
Regarding claim 19, Kamaraj teaches the limitations of claim 18. Kamaraj further teaches wherein each address of the first plurality addresses has a second offset from a different address of the first plurality of addresses. (Kamaraj Fig. 3 and [0012], [0020], and [0040]-[0050], most notably [0042], [0045] discloses there may be a first search using a first midpoint of 341-1 and a second search using a second midpoint between the first midpoint and the first or last addresses of the memory bank 341-1. Each address of the first plurality of addresses is offset to one another by a half of a half of the size of the size of the memory banks. Thus the first address and second address of the address searched in 341-1 has a second offset from the different address of the first plurality of addresses.)
Regarding claim 20, Kamaraj teaches all of the limitations of claim 18. Kamaraj further teaches wherein each address of the second plurality of addresses has the second offset from a different address of the second plurality of addresses. (Kamaraj Fig. 3 and [0012], [0020], and [0040]-[0050], most notably [0042], [0045] discloses there may be a first search using a first midpoint of 341-2 and a second search using a second midpoint between the first midpoint and the first or last addresses of the memory bank 341-2. Each address of the second plurality of addresses is offset to one another by a half of a half of the size of the size of the memory banks. Thus the first address and the second address of the addresses searched in 341-2 (the second plurality of addresses) has a second offset from the different address of the second plurality of addresses.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-16 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Kamaraj (Kamaraj et al., US 2022/0206707 A1) as detailed in claim 9 above and further in view of the Open_NAND_1.0 (Open NAND Flash Interface Specification, Revision 1.0 28-December-2006).
Regarding claim 13, Kamaraj teaches all of the limitations of claim 9 above. However Kamaraj does not explicitly teach address bits, thus does not explicitly teach wherein the first address has a first plurality of bits.
Open_NAND_1.0, of a similar field of endeavor, further discloses wherein the first address has a first plurality of bits. (Kamaraj [0023]-[0024] discloses the memory addresses are accessed via column and row decoders. But does not explicitly these decoders access addresses composed of a plurality of bits. Open_NAND_1.0, page 21, lines 5-30 discloses addresses to flash memory such as the flash memory of Kamaraj [0023]-[0024] is comprised a plurality of address bits. Thus the first address has a first plurality of bits. )
Kamaraj and Open_NAND_1.0 are in a similar field of endeavor as both relate to managing data stored in flash memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the plurality of bits of Open_NAND_1.0 into the solution of Kamaraj. Thus combining prior arts according to known methods (the address definitions of Open_NAND_1.0 to address the NAND memory of Kamaraj) to yield predictable results (enable Kamaraj to access the NAND memory according to a common standard that enable Kamaraj to address a plethora of NAND devices that are designed to support the Open NAND 1.0 standard. )
Regarding claim 14, Kamaraj teaches all of the limitations of claim 11 above. However Kamaraj does not explicitly teach wherein the second address has a second plurality of bits.
Open_NAND_1.0, of a similar field of endeavor, further discloses wherein the second address has a second plurality of bits. (Kamaraj [0023]-[0024] discloses the memory addresses are accessed via column and row decoders. But does not explicitly these decoders access addresses composed of a plurality of bits. Open_NAND_1.0, page 21, lines 5-30 discloses addresses to flash memory such as the flash memory of Kamaraj [0023]-[0024] is comprised a plurality of address bits. Thus the second address has a second plurality of bits.)
The motivation to combine Open_NAND_1.0 into Kamaraj is the same as set forth in claim 13 above.
Regarding claim 15, Kamaraj and Open_NAND_1.0 teaches all of the limitations of claim 14 above.
Open_NAND_1.0 further teaches wherein the first plurality of bits and the second plurality of bits are different. (Kamaraj [0023]-]0024] discloses the first and second address point to separate address targets thus are different. Open_NAND_1.0 page 21, lines 5-30 discloses these two address are a plurality of bits. Thus Kamaraj in view of Open_NAND_1.0 teaches the first plurality of bits and the second plurality of bits point to different address and are different.)
The motivation to combine Open_NAND_1.0 into the existing combination are the same as set forth in claim 13 above.
Regarding claim 16, Kamaraj and Open_NAND_1.0 teaches all of the limitations of claim 15 above. Kamaraj further teaches wherein the initiator device is configured to: provide a first access command corresponding to the first search (Kamaraj [Abstract], [0012], and [claim 4] discloses the memory banks such as 341-1 to 341-3 containing slots are searched in parallel, thus discloses a first access command to 341-1.) via the first port (Kamaraj [0042] discloses each memory bank such as 341-1 is accessed using a data port and an address port, thus via a first port.) … wherein the first access command is for the first address; (Kamaraj [0045] discloses that the search begins at a first midpoint. Kamaraj [0042] discloses that the data within each memory bank is accessed using an address port. Thus the midpoint location that is accessed using a first address. Kamaraj [Abstract], [0012], [0042], and [claim 4] discloses that this command is to 134-1 via a first port is for a first address.)
and provide a second access command corresponding to the second search (Kamaraj [Abstract], [0012], and [claim 4] discloses there may be a second memory bank 341-2 that receives a second access command to search the second bank in parallel to search 41-1) via the second port (Kamaraj [0042] discloses each memory bank such as 341-2 is accessed using an additional data port and an address port, thus via a second port) … wherein the second access commands is for the second address. (Kamaraj [abstract], [0012], [0042] [0045], and claim 4] discloses that a second search command for bank 134-2 is for a second address (given each bank is dedicated to separate addresses).)
a first access command… corresponding to the first plurality of LSBs of the first address, (Open_NAND_1.0, page 21, lines 5-30 discloses addresses to flash memory such as the flash memory of Kamaraj [0023]-[0024] is comprised a plurality of address bits, including a plurality of LSB that make up the Page Address. Thus the first address has a corresponding first plurality of LSBs.)
… a second access command … corresponding to the second plurality of LSBs of the second address (Open_NAND_1.0, page 21, lines 5-30 discloses addresses to flash memory such as the flash memory of Kamaraj [0023]-[0024] is comprised a plurality of address bits, including a plurality of LSB that make up the Page Address. Thus the second address has a corresponding second plurality of LSBs.)
The motivation to combine Open_NAND_1.0 into Kamaraj is the same as set forth in claim 13 above.
Conclusion
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/JANICE M. GIROUARD/Examiner, Art Unit 2138