Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 are rejected under 35 USC § 101 as being directed to a judicial exception without significantly more, consistent with the Aug. 4, 2025 USPTO § 101 Memorandum and MPEP sections 2103 to 2106.07 for guidance on 35 U.S.C. 101.
Under Step 2A, Prong 1 (Judicial Exception), the claims are directed to abstract ideas – namely, generating network graph, mapping graph and configuration files.
Under Step 2A, Prong 2 (Integration into a practical Application), the claim does not integrate the abstract idea into a practical application. Although the preamble and context reference a “memory processing unit (MPU)”, the body does not recite applying the generated configuration files to actually configure or operate a particular MPU; nor does it recite specific hardware constraints (e.g., bank topology, routing fabric, register writes) or a technological improvement to computer functionality or another technology. The recited “API”, “graph processing module”, “mapping module”, and “assembler” are generic functional components performing routine data processing to produce data (or files).
Under Step 2B (Significantly more), the additional elements, individually and in combination do not amount to significantly more than the abstract idea. Using generic computing components (API, modules, assembler) to generate and manipulate graphs and to output configuration files is well-understood, routine, and conventional in the field of software compilation.
Allowable Subject Matter
Claims 1-15 would be allowable if the rejection under 35 USC § 101 is overcome.
During prior art search, examiner did not identify prior art that anticipates or renders obvious independent claims 1 and 6. Accordingly, if the rejection under 35 USC § 101 is overcome, the claims appear allowable on the present record. However, to overcome the rejection under 35 USC § 101, an appropriate amendment is needed so the claims integrate the abstract idea into a practical application tied to the machine and recite significantly more than generic data processing.
The following is an examiner’s statement of reasons for allowance:
Independent Claim 1 identifies the distinct features “a memory processing unit (MPU) configuration method comprising: generating an initial network graph, by an application programming interface, from a neural network model; generating a final network graph, by a graph processing module, from the initial network graph; generating a mapping graph, by a mapping module, from the final network graph; and generating one or more configuration files, by an assembler, from the mapping graph", which are not taught or suggested by the prior art of records.
Independent Claim 6 identifies the distinct features “a processing unit (PU) configuration method comprising: generating a neural network model; generating a network graph from the neural network model; generating a mapping graph from the network graph based on a target processing unit (PU); and generating one or more configuration files from the mapping graph", which are not taught or suggested by the prior art of records.
Response to Arguments
Applicant’s arguments filed on 01/02/2026 have been fully considered but they are not persuasive.
1st Point of Argument : Step 2A, Prong One (Judicial Exception)
Regarding Applicant’s remarks on pages 6-7, Applicant argues that independent claim 1 is directed to a specific improvement in computer-related technology, namely configuration of a memory processing unit (MPU) through a structured, multi-stage graph-based compilation pipeline derived from a neural network model and that the claimed method addresses a problem rooted in computer technology: how to efficiently and correctly translate high-level neural network models into low-level configuration files suitable for execution on a memory processing unit, which has architectural constraints fundamentally different from general-purpose CPUs or GPUs.
In response, Examiner disagrees. The claims, when given their broadest reasonable interpretation, are directed to abstract ideas, namely, generating network graphs, mapping graphs, and configuration files. Specifically, the claims recite generating an initial network graph, generating a final network graph, generating a mapping graph, and generating one or more configuration files, which amount to generating and manipulating information and data representations.
Regarding Applicant’s remarks on page 8, Applicant further argues that the human mind cannot perform the claimed steps. Generating successive network graphs from a neural network model, transforming those graphs via graph processing and mapping modules, and assembling configuration files suitable for configuring an MPU require computer-specific representations, automated graph transformations, and hardware-dependent compilation steps that do not exist in the human mind and cannot be simulated mentally
In response, Examiner disagrees. The claims do not recite specific hardware constraints (e.g., bank topology, routing fabric, register writes) or any particular technological implementation details. Rather, the claims recite generating graphs and configuration files using an “API”, “graph processing module”, “mapping module” and “assembler” which are generic functional components performing routine data processing to produce data (or files).
2nd Point of Argument : Step 2A, Prong Two (Integration into a practical Application)
Regarding Applicant’s remarks on pages 8-9, Applicant arguee that it produces configuration files that are the operative mechanism by which a memory processing unit is configured and enabled to execute a neural network model. The generation of these configuration files is not incidental, it is the end-use technical application of the claimed method.
In response, Examiner disagrees. This argument is not commensurate in scope with the claims. Although the preamble comprises a “memory processing unit (MPU)”, the body does not recite applying the generated configuration files to actually configure or operate a particular MPU. The claims also do not recite memory placement, dataflow, execution locality, or other specific hardware-aware constraints. Accordingly, the claims do not integrate the abstract idea into a practical application, but instead merely use generic computing components to generate and manipulate graphs and to output configuration files.
3rd Point of Argument : Step 2B (Significantly more)
Regarding Applicant’s remarks on page 8, the applicants argue that the independent claim 1 recites a non-conventional arrangement of computational elements that together form a hardware-aware compilation pipeline for MPUs. While APIs, graph processing, and assemblers may be known individually, their claimed combination and ordered interaction to generate MPU-specific configuration files from neural network models is not well-understood, routine, or conventional.
In response, Examiner disagrees. Using generic computing components (API, graph processing module, mapping module, assembler) to generate and manipulate graphs and to output configuration files is well understood, routine, and conventional in the field of software compilation. The claims do not recite any specific arrangement or interaction of these components beyond their generic functional roles. Accordingly, the claims, when considered as a whole, do not amount to significantly more than the abstract idea.
To overcome the rejection under 35 USC § 101, an appropriate amendment is needed so the claims integrate the abstract idea into a practical application tired to the machine and recite significantly more than generic data processing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mohapatra et al. (Pub. No.: US 2020/0134417) “CONFIGURABLE PROCESSOR ELEMENT ARRAYS FOR IMPLEMENTING CONVOLUTIONAL NEURAL NETWORKS”
Considered for teachings related to neural networks and, more particularly, to configurable processor element arrays for implementing convolutional neural networks.
Does not disclose or suggest generating an initial network graph, by an application programming interface, from a neural network model; generating a final network graph, by a graph processing module, from the initial network graph; generating a mapping graph, by a mapping module, from the final network graph; and generating one or more configuration files, by an assembler, from the mapping graph.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 8:00am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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