Prosecution Insights
Last updated: August 18, 2026
Application No. 18/919,270

SYSTEM AND METHOD FOR AGGREGATING SERVER MEMORY

Non-Final OA §DP
Filed
Oct 17, 2024
Priority
Apr 06, 2020 — provisional 63/006,073 +5 more
Examiner
PEYTON, TAMMARA R
Art Unit
2184
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
91%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
876 granted / 964 resolved
+35.9% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
14 currently pending
Career history
978
Total Applications
across all art units

Statute-Specific Performance

§101
9.0%
-31.0% vs TC avg
§103
60.9%
+20.9% vs TC avg
§102
9.3%
-30.7% vs TC avg
§112
4.3%
-35.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 964 resolved cases

Office Action

§DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time wise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,650,944. Although the claims at issue are not identical, they are not patentably distinct from each other because both discloses “a first computing device, comprising: a first switch including a processing device configured to adhere to a cache coherent protocol; a first memory device and a second memory device connected to the first switch, wherein the first memory device is associated with a first memory technology….” Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. application 18/919,270. Instant Application Claim 1, 18/919,270 Claim 1, US Patent 12,650,944 A system comprising: a processing circuit; a cache coherent switch circuit connected to the processing circuit; and a first memory module connected to the cache coherent switch circuit via a memory interface associated with a first memory technology, the processing circuit being connected to the first memory module via the cache coherent switch circuit, and the cache coherent switch circuit being configured to support a cache coherent memory protocol, the cache coherent switch circuit being further configured to: receive a memory access request that adheres to the cache coherent memory protocol; translate the memory access request to a signal that corresponds to the memory interface; and route the signal to the first memory module over the memory interface. A system, comprising: a first computing device, comprising: a first switch including a processing device configured to adhere to a cache coherent protocol; a first memory device and a second memory device connected to the first switch, wherein the first memory device is associated with a first memory technology and the second memory device is associated with a second memory technology different from the first memory technology; and a second switch connected to the first computing device, wherein: the second switch is configured to receive a first data request and a second data request, wherein the first data request and the second data request adhere to the cache coherent protocol, the processing device of the first switch is configured to: identify the first memory device based on the first data request; translate the first data request into a third data request based on the first memory technology, wherein the third data request adheres to a first memory protocol different from the cache coherent protocol; transmit the third data request to the first memory device for accessing the first memory device; identify the second memory device based on the second data request; translate the second data request to a fourth data request based on the second memory technology, wherein the fourth data request adheres to a second memory protocol different from the first memory protocol and the cache coherent protocol; and transmit the fourth data request to the second memory device for accessing the second memory device. Conclusion The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tammara Peyton whose telephone number is (571) 272-4157. The examiner can normally be reached between 8:30- 6:00 from Monday to Thursday, (I am off every first Friday), and 7:30- 4:00 every second Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor Henry Tsai can be reached on (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Any inquiry of a general nature of relating to the status of this application should be directed to the Group receptionist whose telephone number is (571) 272- 2100. /Tammara R Peyton/ Primary Examiner, Art Unit 2184 July 11, 2026
Read full office action

Prosecution Timeline

Show 2 earlier events
Feb 13, 2026
Applicant Interview (Telephonic)
Feb 13, 2026
Examiner Interview Summary
Mar 03, 2026
Response Filed
Apr 08, 2026
Final Rejection mailed — §DP
Jun 08, 2026
Response after Non-Final Action
Jul 01, 2026
Request for Continued Examination
Jul 04, 2026
Response after Non-Final Action
Jul 15, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12675427
PCIE CHANNEL SWITCHES IN DATA TRANSMISSION SYSTEMS
2y 0m to grant Granted Jul 07, 2026
Patent 12675308
DYNAMIC I/O VIRTUALIZATION SYSTEM HAVING GUEST MEMORY MANAGEMENT FOR MAPPING VIRTUAL ADDRESSES USING VIRTUALIZATION APPLICATION PROGRAMMING INTERFACE (API) IN GUEST KERNAL
1y 10m to grant Granted Jul 07, 2026
Patent 12643493
APPLICATION PROFILES IN ELECTRONIC CONTROL UNITS
3y 1m to grant Granted Jun 02, 2026
Patent 12645467
REPROCESSING A REPLACEABLE SUPPLY COMPONENT TO RECONFIGURE AN END-USER DEVICE
2y 9m to grant Granted Jun 02, 2026
Patent 12645465
BOOT RAM FOR SAFETY CRITICAL DOMAIN
2y 8m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+6.0%)
2y 3m (~5m remaining)
Median Time to Grant
High
PTA Risk
Based on 964 resolved cases by this examiner. Grant probability derived from career allowance rate.

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