DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/12/2026 have been fully considered but they are not persuasive. Applicant argues that prior art fails to teach that the original data and the compensation data are received from a host processor through a same transmission interface. Examiner, respectfully, disagrees and addresses that argument in claim 1 below. Applicant argues that prior art fails to explicitly teach a selector, coupled to the transmitter to selectively forward the original image data or stress data to the transmitter. Examiner, respectfully, disagrees and addresses that argument in claim 8 below. Applicant argues that prior art fails to combine deburn-in offset and demura offset value to provide compensation. Examiner, respectfully, disagrees and address that argument in claim 21 below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8, 9, 12, 14, 16, 28, 29, 33, 34, and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. (hereinafter “An”), US Pub. No. 2017/0162103.
Regarding claim 8, An teaches a host processor (fig. 1, processor 110), comprising: a stress accumulator to generate a stress value according to an original image data and accumulate the stress value to generate an accumulated stress value (fig. 1, accumulation block 130); and a transmitter, coupled to the stress accumulator, to send a compensation data corresponding to the accumulated stress value and send the original image data to a display driver circuit (fig. 1, COMPF, RGB); fig. 6); and a selector, coupled to the transmitter, to selectively forward the original image data or the accumulated stress value to the transmitter (Although not explicitly taught, the transmission of the RGB image data and stress data would require a selection or multiplexing of the data. Therefore, a person having ordinary skill in the art would recognize that a selector, multiplexer, or switching mechanism is inherently present to forward the image data or the stress data to the transmitter.
Regarding claim 9, An teaches wherein the compensation data comprises the accumulated stress value (fig. 1, COMPF).
Regarding claim 12, An teaches wherein the compensation data comprises a main offset value and an auxiliary offset value ([0029]; fig. 6).
Regarding claim 14, An teaches a pixel arrangement converter, coupled to the stress accumulator, to convert the original image data into a pixel data corresponding to a display panel controlled by the display driver circuit; wherein the stress accumulator generates the stress value according to the pixel data ([0029]).
Regarding claim 16, An teaches wherein the stress accumulator accumulates the stress value by taking a pixel or a subpixel as a unit ([0029]).
Regarding claim 29, An teaches wherein the compensation data comprises the accumulated stress value ([0028]).
Regarding claim 33, An teaches wherein the second transmitter sends the compensation data by accessing a memory of the display driver circuit (fig. 11, stress input block 675, compensation factor block 680).
Regarding claim 34, it has similar limitations to those of claim 14 and is rejected on the same grounds presented above.
Regarding claim 36, it has similar limitations to those claim 16 and is rejected on the same grounds presented above.
Claims 21, 22, 26, and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shikata et al. (hereinafter “Shikata”), US Pub. No. 2023/0222958.
Regarding claim 21, Shikata teaches a display driver circuit (fig. 1, display driver 112), comprising a receiver to receive an original image data from a host processor through a first interface (fig. 1, image processing module 160, image data 157); a memory to receive a compensation data from the host processor through a second interface, and store the compensation data (fig. 1, memory 110); and a compensation circuit, coupled to the memory and the receiver, to read out the compensation data from the memory (fig. 1, compensation controller 140), and compensate the original image data by using the compensation data to generate a first compensated image data ([0039]); wherein the compensation data comprises a deburn-in offset value, and the compensation circuit compensates the original image data by combining the deburn-in offset value with a demura offset value (fig. 2; in particular Shikata teaches demura and deburn in a time-division application. Fig. 2 shows that multiple compensation datasets are provided and used within the same display operation. A person having ordinary skill in the art would understand that applying multiple compensation values sequentially to the same pixel data results in a cumulative compensation effect. Functionally, Shikata reads on the claimed limitation of combining demura and deburn in offsets to produce a compensated image. The claim language does explicitly require direct arithmetic summation or simultaneous combination in a single operation).
Regarding claim 22, Shikata teaches wherein the compensation data comprises a deburn-in offset value ([0029, 0039], deburn compensation).
Regarding claim 26, Shikata teaches wherein the compensation data comprises a deburn-in offset value, and the compensation circuit compensates the original image data by using the deburn-in offset value and a demura offset value ([0030]).
Regarding claim 27, Shikata teaches wherein the compensation circuit compensates the original image data by using the deburn-in offset value to generate the first compensated image data, and compensates the first compensated image data by using the demura offset value to generate a second compensated image data ([0039]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 10, 11, 13, 15, 17-20, 23-25, 28, 30-32, 35, and 37-40 are rejected under 35 U.S.C. 103 as being unpatentable over Shikata (see above), in view of An (see above).
Regarding claim 1, Shikata teaches a display driver circuit (fig. 1, display driver 112), comprising: a receiver (fig. 1, image processing module 160) to receive an original image data from a host processor (fig. 1, image data 157); a memory to store the compensation data (fig. 1, non-volatile memory 110); and a compensation circuit (fig. 1, image compensation controller 140), coupled to the memory (memory 110) and the receiver (image processing module 160), and compensate the original image data by using the compensation data to generate a first compensated image data ([0039]).
Shikata fails to explicitly teach wherein the receiver receives an original image data and a compensation data from a host processor through a same transmission interface.
However, in the same field of endeavor, An teaches a compensation method wherein a host processor transmits original image data in addition to a compensation factor (see fig. 1, image data RGB and compensation factor COMPF coming from display controller; in particular the RGB and COMP signals are transmitted via a common transmission interface between the processor and the OLED device).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Shikata to include the feature of An. As such, one would appreciate the motivation for doing so would have been to decrease degradation in a display device (An, [0003]).
Regarding claim 2, Shikata teaches wherein the compensation data comprises an accumulated stress value or a deburn-in offset value ([0028]).
Regarding claim 3, the combination of Shikata and An teaches a stress-to-offset converter, coupled to the memory, to convert the accumulated stress value into a deburn-on offset value (Shikata, [0029]; An, accumulation block 130, COMPF).
Regarding claim 4, Shikata teaches wherein the compensation data comprises a deburn-in offset value, and the compensation circuit compensates the original image data by using the deburn-in offset value and a demura offset value ([0030]).
Regarding claim 5, Shikata teaches wherein the compensation circuit compensates the original image data by using the deburn-in offset value to generate the first compensated image data, and compensates the first compensated image data by using the demura offset value to generate a second compensated image data ([0039]).
Regarding claim 6, An teaches wherein the compensation data comprises a main offset value, and the compensation circuit compensates the original image data by using the main offset value and an auxiliary offset value ([0029]; fig. 6).
Regarding claim 7, Shikata teaches wherein the main offset value is obtained in a first frequency and the auxiliary offset value is obtained in a second frequency greater than the first frequency ([0026]).
Regarding claim 10, it has similar limitations to those of claim 3 and is rejected on the same grounds presented above.
Regarding claim 11, it has similar limitations to those of claim 4 and is rejected on the same grounds presented above.
Regarding claim 13, it has similar limitations to those of claim 7 and is rejected on the same grounds presented above.
Regarding claim 15, Shikata teaches wherein the stress accumulator further receives a demura offset value, and generates the stress value according to a compensated image data which is generated from the original image data compensated by the demura offset value ([0030]).
Regarding claim 17, it is a combination of independent claims 1 and 8, and is rejected on the same grounds presented above.
Regarding claim 18, it has similar limitations to those of claim 2 and is rejected on the same grounds presented above.
Regarding claim 19, it has similar limitations to those of claim 4 and is rejected on the same grounds presented above.
Regarding claim 20, it has similar limitations to those of claim 11 and is rejected on the same grounds presented above.
Regarding claim 23, the combination of Shikata and An teaches wherein the first interface is a mobile industry processor interface (An, [0026])), and the second interface is a serial peripheral interface (Shikata, [0024]).
Regarding claim 24, An teaches wherein the compensation data is sent to the memory by the host processor without [going] through the receiver (fig. 1, processor 110, memory 140).
Regarding claim 25, it has similar limitations to those of claim 3 and is rejected on the same grounds presented above.
Regarding claim 28, An teaches a host processor (fig. 1, processor 110), comprising: a stress accumulator to generate a stress value according to an original image data and accumulate the stress value to generate an accumulated stress value (fig. 1, accumulation block 130); and a first transmitter to send the original image data to a display driver circuit (fig. 1, RGB); and a second transmitter, coupled to the stress accumulator, to send a compensation data corresponding to the accumulated stress value to the display driver circuit (fig. 1, accumulation block 130, COMPF).
An fails to explicitly teach wherein the stress accumulator further receives a demura offset value, and generates the stress value according to a compensated image data which is generated from the original image data compensated by the demura offset value.
However, in the same field of endeavor, Shikata teaches wherein the compensation data comprises a deburn-in offset value, and the compensation circuit compensates the original image data by combining the deburn-in offset value with a demura offset value (fig. 2; in particular Shikata teaches demura and deburn in a time-division application. Fig. 2 shows that multiple compensation datasets are provided and used within the same display operation. A person having ordinary skill in the art would understand that applying multiple compensation values sequentially to the same pixel data results in a cumulative compensation effect. Functionally, Shikata reads on the claimed limitation of combining demura and deburn in offsets to produce a compensated image. The claim language does explicitly require direct arithmetic summation or simultaneous combination in a single operation).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify An to include the feature of Shikata. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to decrease degradation in a display device.
Regarding claim 30, it has similar limitations to those of claim 3 and is rejected on the same grounds presented above.
Regarding claim 31, the combination of Shikata and An teaches wherein the stress accumulator further receives the deburn-in offset value, and generates the stress value according to a compensated image data which is generated from the original image data compensated by the deburn-in offset value (Shikata, deburn compensation, [0029]; An, fig. 1, stress accumulation block 130).
Regarding claim 32, it has similar limitations to those of claim 23 and is rejected on the same grounds presented above.
Regrading claim 35, it has similar limitations to those of claim 15 and is rejected on the same grounds presented above.
Regarding claim 37, it is a combination of independent claims 21 and 28, and is rejected on the same grounds presented above.
Regarding claim 38, An teaches wherein the compensation data comprises accumulated stress value (fig. 1, COMPF, accumulated stress block 130).
Regarding claim 39, it has similar limitations to those of claim 4 and is rejected on the same grounds presented above.
Regarding claim 40, it has similar limitations to those of claim 11 and is rejected on the same grounds presented above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yum et al. (US Pub. No. 2019/0340980) teaches a display driver system including a host processor transmitting image data to a display driver with a compensator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B LEE JR whose telephone number is (571)270-3147. The examiner can normally be reached Mon - Fri 9am-5pm.
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625