DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-28 are presented for examination.
The claims and only the claims form the metes and bounds of the invention. “Office personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Limitations appearing in the specification but not recited in the claim are not read into the claim. In re Prater, 415 F.2d 1393, 1404-05, 162 USPQ 541, 550-551 (CCPA 1969)” (MPEP p 2100-8, c 2, I 45-48; p 2100-9, c 1, l 1-4). The Examiner has full latitude to interpret each claim in the broadest reasonable sense. The Examiner will reference prior art using terminology familiar to one of ordinary skill in the art. Such an approach is broad in concept and can be either explicit or implicit in meaning.
Response to Arguments
Applicant’s remarks/amendment was filed on 02 February 2026.
US PGPUB 2009/0327818 by Kogelnik, US PGPUB 6,320,523 by York et al., and US PGPUB 2022/0094767 by Lehmann et al. are newly introduced for the rejection of the amended claims.
Applicant’s arguments have been considered but they are moot in view of new ground(s) of rejection. However, the Examiner welcomes any suggestion(s) Applicant may have on moving prosecution forward. The Examiner’s contact information is in the Conclusion of this office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5, 7-8, 11, 13-16, 19, 21-22, 25 and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2009/0327818 by Kogelnik in view of US PGPUB 6,320,523 by York et al. (“York”) and further in view of in view of US PGPUB 2022/0094767 by Lehmann et al. (“Lehmann”).
As to Claim 1, Kogelnik teaches a system for optimizing intrachip communication using machine learning, comprising: a multi-core processing chip comprising a plurality of processing cores (Kogelnik: at least ¶0040; “multi-core security encryption (SEP) processor”), wherein at least one processing core of the plurality of processing cores comprises:
firmware (Kogelnik: at least ¶¶0041-0042; “the logic implemented by the FPGA may be embodied in an Application Specific Integrated Circuit (ASIC), or the like, in a secure software environment, software/hardware combination, etc.” and “FPGA configured to perform encryption and decryption operations for the SEP”);
a processor (Kogelnik: at least ¶¶0041-0042; “multi-core security encryption (SEP) processor”);
a codebook embedded in the firmware (Lehmann: at least ¶0042; “the FPGA can be configured to include multiple processing cores such an encryption core 310, a decryption core 320, a compression core 340, and a decompression core 350”; note: LZW makes use of a dictionary or codebook); and
a plurality of programming instructions stored in the firmware and operable on the
processor (Kogelnik: at least ¶¶0041-0042; “the logic implemented by the FPGA may be embodied in an Application Specific Integrated Circuit (ASIC), or the like, in a secure software environment, software/hardware combination, etc.” and “FPGA configured to perform encryption and decryption operations for the SEP”), wherein the plurality of programming instructions, when operating on the processor, causes the multi-core processing chip to: collect data on codebook usage during intrachip communication (Kogelnik: at least ¶¶0043, 0053; “the compression core 340 compresses blocks of data” and “compression core 630” and “plaintext data 650 is compressed. Various compression and decompression algorithms can be used, such as using Lempel-Ziv-Welch (LZW) compression”; ¶0057 further discloses “parallel encryption process can be combined with compression and decompression cores using checksums to detect errors”; note: LZW makes use of a dictionary or codebook; data on whether codebook usage has errors), wherein intrachip communication comprises encoding data using the codebook on a first processing core of the multi-core processing chip (Kogelnik: at least ¶¶0043, 0053; “encryption core 310 performs encryption of blocks of data” and “the compression core 340 compresses blocks of data” and “compression core 630” and “plaintext data 650 is compressed. Various compression and decompression algorithms can be used, such as using Lempel-Ziv-Welch (LZW) compression”; note: LZW uses a dictionary or codebook) and transmitting encoded data to a second processing core of the multi-core processing chip (Kogelnik: at least ¶0054; “… then subsequently decompressed by the decompression core 640 to produce the plaintext data 650”).
Kogelnik does not explicitly disclose, but York discloses wherein the codebook comprises sourceblocks each with a pattern of bits and a reference code unique within the codebook (York: at least Col. 1 Lines 65-67; “optimize the speed of data compression implemented with the use of a string dictionary”; Col. 2 Lines 37-39 further disclose “store a unique single string code value of fewer bits in a dictionary that is representative of the string of characters contained in the unique pointer address code of greater bits”; Claim 1 also discloses “storing unique code values for new strings in said dictionary”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate York’s feature of wherein the codebook comprises sourceblocks each with a pattern of bits and a reference code unique within the codebook (York: at least Col. 1 Lines 65-67, Col. 2 Lines 37-39, Claim 1) with Kogelnik’s system.
The suggestion/motivation for doing so would have been to “optimize the speed of data compression implemented with the use of a string dictionary” (York: at least Col. 1 Lines 65-67)
Lehmann also discloses collect data on codebook usage during intrachip communication (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated”; note: collect performance data).
Kogelnik and York do not explicitly disclose, but Lehmann discloses a machine learning model embedded in the firmware and executing on the processor (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated, and if the compression performance is detected to be below a threshold …”);
extract features from the collected data (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated”; note: collect and extract performance from performance data);
analyze the extracted features using the machine learning model to recommend codebook updates (Lehmann: at least ¶0021; “if the compression performance is detected to be below a threshold … rebuilding of the pre-shared compression dictionary is triggered”);
implement the recommended updates to the codebook (Lehmann: at least ¶0021; “… rebuilding of the pre-shared compression dictionary is triggered”);
monitor performance metrics to evaluate the effectiveness of the updates (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated, and if the compression performance is detected to be below a threshold …”); and
adjust codebook refinement process based on monitored performance metrics (Lehmann: at least ¶0021; “if the compression performance is detected to be below a threshold (e.g., a new log input stream is introduced), rebuilding of the pre-shared compression dictionary is triggered”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lehmann’s features of a machine learning model embedded in the firmware and executing on the processor (Lehmann: at least ¶0021); extract features from the collected data (Lehmann: at least ¶0021);
analyze the extracted features using the machine learning model to recommend codebook updates (Lehmann: at least ¶0021);
implement the recommended updates to the codebook (Lehmann: at least ¶0021);
monitor performance metrics to evaluate the effectiveness of the updates (Lehmann: at least ¶0021); and
adjust codebook refinement process based on monitored performance metrics (Lehmann: at least ¶0021) with the system disclosed by Kogelnik and York.
The suggestion/motivation for doing so would have been to ensure desirable performance in compression process (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated, and if the compression performance is detected to be below a threshold”).
Claim 15 (a method claim) corresponds in scope to Claim 1, and are similarly rejected.
As to Claim 2, Kogelnik, York and Lehmann teach the system of claim 1, wherein the data collection is performed continuously during intrachip communication (Kogelnik: at least ¶¶0043, 0053; “the compression core 340 compresses blocks of data” and “compression core 630” and “plaintext data 650 is compressed. Various compression and decompression algorithms can be used, such as using Lempel-Ziv-Welch (LZW) compression”; ¶0057 further discloses “parallel encryption process can be combined with compression and decompression cores using checksums to detect errors”; note: LZW makes use of a dictionary or codebook; data on whether codebook usage has errors).
Claim 16 (a method claim) corresponds in scope to Claim 2, and are similarly rejected.
As to Claim 5, Kogelnik, York and Lehmann teach the system of claim 1, wherein the implementation of recommended updates to the codebook occurs in real-time, thereby adapting the codebook to evolving data patterns (Lehmann: at least ¶0021; “… rebuilding of the pre-shared compression dictionary is triggered”).
Claim 19 (a method claim) corresponds in scope to Claim 5, and are similarly rejected.
As to Claim 7, Kogelnik, York and Lehmann teach the system of claim 1, wherein the plurality of programming instructions further cause the multi-core processing chip to maintain system stability by implementing gradual updates to the codebook (Lehmann: at least ¶0021; “if the compression performance is detected to be below a threshold (e.g., a new log input stream is introduced), rebuilding of the pre-shared compression dictionary is triggered”), wherein the rate of the gradual updates are dynamically adjusted based on monitored performance metrics (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated” and “if the compression performance is detected to be below a threshold …”).
Claim 21 (a method claim) corresponds in scope to Claim 7, and are similarly rejected.
As to Claim 8, Kogelnik, York and Lehmann teach the system of claim 1, wherein the plurality of programming instructions further cause the multi-core processing chip to provide a fallback mechanism to a pre-trained, conservative codebook during initial operation or if performance falls below a threshold (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated” and “if the compression performance is detected to be below a threshold …”).
Claim 22 (a method claim) corresponds in scope to Claim 8, and are similarly rejected.
As to Claim 11, Kogelnik, York and Lehmann teach the system of claim 1, wherein the machine learning model is incrementally trained using the collected data, allowing for ongoing adaptation to changing data patterns without the need for offline retraining (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated, and if the compression performance is detected to be below a threshold …”).
Claim 25 (a method claim) corresponds in scope to Claim 11, and are similarly rejected.
As to Claim 13, Kogelnik, York and Lehmann teach the system of claim 1, wherein the plurality of programming instructions further cause the multi-core processing chip to use synthetic data generation techniques to augment training data during initial system operation (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated).
Claim 27 (a method claim) corresponds in scope to Claim 13, and are similarly rejected.
As to Claim 14, Kogelnik, York and Lehmann teach the system of claim 1, wherein the plurality of programming instructions further cause the multi-core processing chip to implement an anomaly detection mechanism to identify potential security threats based on unusual patterns in codebook usage or update requests (Lehmann: at least ¶0021; “the compression performance of the pre-shared dictionary is continuously evaluated, and if the compression performance is detected to be below a threshold …”).
Claim 28 (a method claim) corresponds in scope to Claim 14, and are similarly rejected.
Claims 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2009/0327818 by Kogelnik in view of US PGPUB 6,320,523 by York et al. (“York”) and further in view of in view of US PGPUB 2022/0094767 by Lehmann et al. (“Lehmann”), and further in view of US Patent 7,644,108 by Malmskog.
As to Claim 3, Kogelnik, York and Lehmann teach the system of claim 1.
Kogelnik, York and Lehmann do not explicitly disclose, but Malmskog discloses wherein the features extracted from the collected data include frequency of codeword usage, patterns of unmatched sourceblocks, and temporal patterns of data transmission (Malmskog: at least Col. 8 Lines 22-24 & Col. 9 Lines 36-39; “Cache 34 receives the query and performs the cache lookup to determine whether the requested content resides within cache 34” and “cache statistics 50 may store statistical information relevant to the cache, such as the number and frequency of cache misses, the number and frequency of cache hits, and other such statistical information relevant to cache 34”; Col. 5 Lines 30-32 also disclose “simultaneously cache and intelligently serve different historical versions of network content”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Malmskog’s feature of wherein the features extracted from the collected data include frequency of codeword usage, patterns of unmatched sourceblocks, and temporal patterns of data transmission (Malmskog: at least Col. 5 Lines 30-32, Col. 8 Lines 22-24, Col. 9 Lines 36-39) with the system disclosed by Kogelnik, York and Lehmann.
The suggestion/motivation for doing so would have been “to facilitate efficient operation of cache” (Malmskog: at least Col. 8 Lines 31-34).
Claim 17 (a method claim) corresponds in scope to Claim 3, and are similarly rejected.
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2009/0327818 by Kogelnik in view of US PGPUB 6,320,523 by York et al. (“York”) and further in view of in view of US PGPUB 2022/0094767 by Lehmann et al. (“Lehmann”), and further in view of US PGPUB 2012/0041914 by Tirunagari et al. (“Tirunagari”).
As to Claim 4, Kogelnik, York and Lehmann teach the system of claim 1.
Kogelnik, York and Lehmann do not explicitly disclose, but Tirunagari discloses wherein the machine learning model is designed for efficient execution within the constraints of on-chip resources (Tirunagari: at least ¶0019; “neural networks may be used to model complex relationships between inputs and outputs (e.g., as non-linear statistical models), and can learn by example. Therefore, the use of neural networks may allow certain types of tasks to be performed in a manner that is both flexible and powerful. The systems and methods described herein may in some embodiments be used to apply neural networks to the task of designing an efficient cache, which may be referred to as a "neural cache". For example, in some embodiments, neural networks may be used to model the relationships between performance related inputs and outputs in the system in order to iteratively and dynamically select a suitable caching algorithm for a given application, resource request, and/or execution context (e.g., hardware and/or operating system configuration) during runtime”; ¶0055 further discloses “they may be applied to select a replacement policy for data stored in a level 1 (L1) or level 2 (L2) cache within a processor, in an on-chip or off-chip level 3 (L3) cache”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Tirunagari’s feature of wherein the machine learning model is designed for efficient execution within the constraints of on-chip resources (Tirunagari: at least ¶¶0019, 0055) with the system disclosed by Kogelnik, York and Lehmann.
The suggestion/motivation for doing so would have been to “select a caching algorithm likely to improve performance of the application” (Tirunagari: at least ¶0006).
Claim 18 (a method claim) corresponds in scope to Claim 4, and are similarly rejected.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2009/0327818 by Kogelnik in view of US PGPUB 6,320,523 by York et al. (“York”) and further in view of in view of US PGPUB 2022/0094767 by Lehmann et al. (“Lehmann”), and further in view of US PGPUB 2020/0128307 Li, and further in view of US PGPUB 2014/0136147 by Cashman et al. (“Cashman”).
As to Claim 6, Kogelnik, York and Lehmann teach the system of claim 1.
Kogelnik, York and Lehmann do not explicitly disclose, but Li discloses wherein the monitored performance metrics include compression ratio and encoding/decoding speed (Li: at least ¶0202; “primary performance metrics produced by the testing software can include compression ratio, compression rate, encoding speed, and decoding speed”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Li’s feature of wherein the monitored performance metrics include compression ratio and encoding/decoding speed (Li: at least ¶0202; “primary performance metrics produced by the testing software can include compression ratio, compression rate, encoding speed, and decoding speed”) with the system disclosed by Kogelnik, York and Lehmann.
The suggestion/motivation for doing so would have been to perform testing of framework for data compression (Li: at least ¶0202).
Kogelnik, York, Lehmann and Li do not explicitly disclose, but Cashman discloses wherein the monitored performance metrics include frequency of codebook misses (Cashman: at least ¶0024; “where each read that requires a fetch from storage is considered a miss and otherwise a hit. A performance metric might be the ratio of read hits to the total read IOs. The output would then be 100% as a maximum and that is also the maximum achievable value in the current configuration and the current value is the ratio above as a percentage. A similar algorithm could be applied to writes. A hit is where there is sufficient cache to allow the write to occur and a miss is where data has to be de-staged to actual storage in order to create space for the write. Once again a ratio or percentage could be used to reflect efficiency”; ¶0030 also discloses “measuring performance can also be applied to databases”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Cashman’s feature of wherein the monitored performance metrics include frequency of codebook misses (Cashman: at least ¶¶0024, 0030) with the system disclosed by Kogelnik, York, Lehmann and Li.
The suggestion/motivation for doing so would have been to determine system performance in a system comprised of one or more components (Cashman: at least ¶0003).
Claim 20 (a method claim) corresponds in scope to Claim 6, and are similarly rejected.
Claims 9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2009/0327818 by Kogelnik in view of US PGPUB 6,320,523 by York et al. (“York”) and further in view of in view of US PGPUB 2022/0094767 by Lehmann et al. (“Lehmann”), and further in view of in view of US PGPUB 2022/0014466 by Doshi et al. (“Doshi”).
As to Claim 9, Kogelnik, York and Lehmann teach the system of claim 1.
Kogelnik, York and Lehmann do not explicitly disclose, but Doshi discloses wherein the plurality of programming instructions further cause the multi-core processing chip to implement a secure update mechanism using cryptographic signatures to prevent unauthorized codebook modifications (Doshi: at least ¶0067; “data object A 605 may be compressed, and then its compression dictionary may be encrypted” and “encryption key”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Doshi’s feature of wherein the plurality of programming instructions further cause the multi-core processing chip to implement a secure update mechanism using cryptographic signatures to prevent unauthorized codebook modifications (Doshi: at least ¶0067; “data object A 605 may be compressed, and then its compression dictionary may be encrypted” and “encryption key”) with the system disclosed by Kogelnik, York and Lehmann.
The suggestion/motivation for doing so would have been to prevent “users from having their information updates to be perform “light encryption” on data that “may have temporal value” and “will mean little in a short period of time” (Doshi: at least ¶0068).
Claim 23 (a method claim) corresponds in scope to Claim 9, and are similarly rejected.
Claims 10 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2009/0327818 by Kogelnik in view of US PGPUB 6,320,523 by York et al. (“York”) and further in view of in view of US PGPUB 2022/0094767 by Lehmann et al. (“Lehmann”), and further in view of US PGPUB 2017/0083074 by Piga et al. (“Piga”).
As to Claim 10, Kogelnik, York and Lehmann teach the system of claim 1.
Kogelnik, York and Lehmann do not explicitly disclose, but Piga discloses wherein the plurality of programming instructions further cause the multi-core processing chip to optimize power consumption by adjusting the codebook refinement process based on the current power state of the multi-core processing chip (Piga: at least ¶0027; “runtime system 201 may increase the power consumption of the processor 104 by modifying one or more of the parameters in the database 103b to change power states, then executing the task in the processor 104 while operating the processor 104 according to the modified parameters”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Piga’s feature of wherein the plurality of programming instructions further cause the multi-core processing chip to optimize power consumption by adjusting the codebook refinement process based on the current power state of the multi-core processing chip (Piga: at least ¶0027) with the system disclosed by Kogelnik, York and Lehmann.
The suggestion/motivation for doing so would have been to allow “dynamically balance power consumption and performance according to the user's satisfaction” (Piga: at least ¶0011).
Claim 24 (a method claim) corresponds in scope to Claim 10, and are similarly rejected.
Claims 12 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB 2009/0327818 by Kogelnik in view of US PGPUB 6,320,523 by York et al. (“York”) and further in view of in view of US PGPUB 2022/0094767 by Lehmann et al. (“Lehmann”), and further in view of US Patent 10,447,296 by Sofia et al. (“Sofia”).
As to Claim 12, Kogelnik, York and Lehmann teach the system of claim 1.
Kogelnik, York and Lehmann do not explicitly disclose, but Sofia discloses wherein the plurality of programming instructions further cause the multi-core processing chip to implement a multi-level codebook system, wherein different codebooks are optimized for different types of data or different processing cores of the multi-core processing chip, and are selected dynamically based on the current communication context (Sofia: at least Col. 10 Lines 24-39; “select a particular compression dictionary compression dictionaries 304a, 304a, 304b, 304c, 304n based on the type of data or data stream to be compressed be compressed. In another embodiment, the dictionary manager 302 can actively learn which compression dictionary compression dictionaries 304a, 304b, 304c, 304n. For example, the OS 215 can store in memory a history of compression ratios that result from using different compression dictionaries with different types of data or data streams. The dictionary manager 302 can predict the compression ratio that may result from using a particular compression dictionary by referring to the compression ratio history for a given data type. Based on the predicted compression ratio, the dictionary manager 302 can select the compression dictionary 304a, 304b, 304c, 304n that provides to the most optimal compression ratio for a given type of data or data stream to be compressed”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sofia’s feature of wherein the plurality of programming instructions further cause the multi-core processing chip to implement a multi-level codebook system, wherein different codebooks are optimized for different types of data or different processing cores of the multi-core processing chip, and are selected dynamically based on the current communication context (Sofia: at least Col. 10 Lines 24-39) with the system disclosed by Kogelnik, York and Lehmann.
The suggestion/motivation for doing so would have been to select “the correct compression dictionary from among the various different available compression dictionaries stored in the dictionary library” (Sofia: at least Col. 11 Lines 40-42).
Claim 26 (a method claim) corresponds in scope to Claim 12, and are similarly rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Huen Wong whose telephone number is (571) 270-3426. The examiner can normally be reached on Monday - Friday (10:30AM EST - 6:30PM EST). If attempts to reach the examiner by telephone are unsuccessful, the Examiner's supervisor, Charles Rones can be reached on (571) 272-4085. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300 for regular communications and after final communications.
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/H .W./
Examiner, AU 2168
02 June 2026
/CHARLES RONES/Supervisory Patent Examiner, Art Unit 2168
Prosecution Insights