Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 15, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9-10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Onodera (US 2006/0238450) in view of Saito et al (US 2008/0084366).
As per claim 9 Onodera discloses: A display device, comprising: a TFT substrate 92/93 including a video signal line 6 formed on a display area, a selecting circuit 44 as a selector circuit that is connected to the video signal line 6 {figure 6}, an inspection circuit 80-82 {figure 3}, and a terminal area {figures 3 & 6};
a counter substrate 91 / 93 {figure 6}; and
a flexible wiring circuit substrate 41,
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wherein the counter substrate 91 / 93 includes a first edge extending in a first direction and a second edge extending in a second direction perpendicular to the first direction,
the flexible wiring circuit substrate 41 includes a third edge extending in the first direction,
the first edge and the third edge face each other, and
the inspection circuit 80-82 is located between the first edge and the third edge {figures 5-6},
the TFT substrate further includes an selecting circuit 44 and the inspection circuit 80-82, and the inspection circuit 80-82 is positioned between the second edge and the selecting circuit 44.
Regarding claim 9 Onodera is silent as to: an organic passivation film. With respect to claim 9 Saito et al discloses: [0088] An organic passivation film 109 is formed on the inorganic passivation film 108 for leveling a surface of the inorganic passivation film 108. Through holes are formed in the inorganic passivation film 108 and the organic passivation film 109 for electrically connecting the source/drain wiring layers 107 and the pixel electrodes 110 and, thereafter, transparent electrodes ITO which constitute the pixel electrodes 110 are formed by sputtering. The pixel electrode 110 can be formed by patterning the transparent electrodes ITO.
It would have been obvious to a person having ordinary skill in the art at the time the invention was effectively filed to provide the display device of Onodera with an organic passivation film as taught by Saito et al. The rationale is as follows: one of ordinary skill in the art at the time the invention was effectively filed would have been motivated to provide a display device with an organic passivation film “for leveling a surface of the inorganic passivation film 108 . . . and . . . electrically connecting the source/drain wiring layers 107 and the pixel electrodes 110”, as well as, to protect the circuits. See [0087] - [0088] of Saito et al.
As per claim 10 Onodera discloses: The display device of claim 9, wherein the inspection circuit 80-82 is positioned adjacent to the second edge {figure 3}.
As per claim 11 Onodera discloses: The display device of claim 9, wherein the TFT substrate 92/93 further includes an selecting circuit 44 and the inspection circuit 80-82.
As per claim 12 Onodera discloses: The display device of claim 9, wherein the inspection circuit 80-82 is connected to the selecting circuit 44 by wirings via a tilted wiring region, and the tilted wiring region extends to the terminal area {figure 6}.
As per claim 13 Onodera discloses: The display device of claim 12, wherein the inspection circuit 80-82 includes an inspection switch arrayed in the first direction, the selecting circuit 44 includes a plurality of switches arrayed in the first direction, the terminal area includes a plurality of signal terminals, and the wirings and the plurality of switches are connected near the plurality of signal terminals. { [0087] In the second embodiment, since the switching circuit 44a is provided in the source circuit 44, in the process of testing a state of a display panel of the liquid crystal device 200, a probe comes into contact with one testing terminal 14a such that a predetermined voltage is applied to one testing terminal 14a, and thus the state of the display panel can be tested without the probe coming into contact with the respective terminals of all of the source lines 6.} Also see [0088].
Response to Arguments
Applicant's arguments filed January 15, 2026 have been fully considered but they are not persuasive. In the ultimate paragraph on page 5 applicant asserts the following:
Applicant traverses those grounds for rejection with respect to the clarified claim features. Applicant submits Onodera is silent with respect to the specific position of the "inspection circuit" and does not disclose or suggest the clarified claim features of "the inspection circuit is positioned between the second edge [of the counter substrate] and the selecting circuit". That is, Onodera does not disclose or suggest that the cited inspection circuit 80-82 is positioned between a second edge of the cited counter substrate 93 and the cited selecting circuit 44. Applicant submits at least those clarified claim features distinguish over Onodera.
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As mapped supra and shown in marked up figure 5, the applied prior shows the claimed invention including the newly added limitation: “the inspection circuit is positioned between the second edge and the selecting circuit.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID D DAVIS whose telephone number is (571)272-7572. The examiner can normally be reached Monday - Friday, 8 a.m. - 4 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID D DAVIS/Primary Examiner, Art Unit 2627
DDD