DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claim(s) 2, 6-8 and 23-27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 16, 2026.
Drawings
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Figure 1: Examiner annotated fig. 5 of applicant’s present disclosure. The up/down direction should be the “THIRD DIRECTION”. Note that the “THIRD DIRECTION” points down to be consistent with the given IV-IV’ view. The same correction should be applied to Fig. 6 of the applicant’s present disclosure.
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Figure 2: Examiner annotated fig. 24 of applicant’s present disclosure. The up/down axis has been labeled to read “Third Direction” and placed to point down in order to be more consistent with fig. 21. The third direction may also point upward but would be less consistent with the previous figures in applicant’s disclosure.
The drawings are objected to because the up/down axis in figs. 5-6 and 24 are incorrectly labeled as “FIRST DIRECTION”. Note that the up/down axis in fig. 25 is possibly labeled incorrectly but cannot be said for sure as no specific view (e.g., IV-IV’) is given. It is noted that a down direction as the “THIRD DIRECTION” would be most consistent with previous figures in the applicant’s disclosure. See present office action figures 1-2 above for additional clarity on the objection.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
111a in at least paras. [0164] and [0168] (it appears it should read as 211a in the specification),
111b in at least para. [0165] (it appears it should read as 211b in the specification), and
300d in at least para. [00197] (it appears it should read as 200d in the specification)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
A (in at least figs. 2 & 7A),
B (in at least figs. 2 & 7B), and
C (in at least figs. 2 & 7C).
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim(s) 32 is/are objected to because of the following informalities:
In claim 32, “the first connection vias penetrating” should read “first connection vias penetrating” as this is the first time “first connection vias penetrating” are being introduced. This technically creates a lack of sufficient antecedent basis.
In claim 32, “the second connection vias penetrating” should read “second connection vias penetrating” as this is the first time “second connection vias penetrating” are being introduced. This technically creates a lack of sufficient antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 33-36 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 33, “a body” is mentioned multiple times and it is unclear if applicant intends to refer to the body introduced in claim 28 or multiple alternative bodies. Furthermore “the margin portions” lacks sufficient antecedent basis and should read “the margin portion”. For purposes of examination, claim 33 is being interpreted as
“The multilayer electronic component of claim 31, wherein the body further comprises the cover portions.”
Claims 34-36 are rejected due to their dependence on claim 33.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 10-15, and 21-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. JP 2010041004 A.
Regarding claim 1, Sato ‘004 discloses
A multilayer electronic component, comprising: a body (1- fig. 4; para. [0037]) including a dielectric layer (VL – fig. 5; para. [0017-0018]) and first and second internal electrodes disposed alternately in a first direction with the dielectric layer therebetween (11, 21 – fig. 5; para. [0040]), and including a first surface and a second surface opposing each other in the first direction (S1, S2, Z – fig. 5), a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction (left, right, X – fig. 5), and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposing each other in a third direction (left right, Y – figs. 6); first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively (first: 5 and/or 7, second: 6 and/or 8 – figs. 4-6 or figs. 9-11); first via electrodes penetrating the dielectric layer and connecting two first internal electrodes adjacent to each other in the first direction (13 – fig. 5; para. [0049]); and second via electrodes penetrating the dielectric layer and connecting two second internal electrodes adjacent to each other in the first direction (23 – fig. 5; para. [0049]), wherein two first via electrodes adjacent to each other in the first direction are shifted from each other, and two second via electrodes adjacent to each other in the first direction are shifted from each other (fig. 5).
Regarding claim 3, Sato ‘004 discloses
The multilayer electronic component of claim 1, wherein a plurality of first via electrodes and a plurality of second via electrodes, penetrating a same dielectric layer, are provided (figs. 5-6).
Regarding claim 4, Sato ‘004 discloses
The multilayer electronic component of claim 3, wherein the plurality of first and second via electrodes penetrating the same dielectric layer are arranged in the second and third directions (figs. 5-6).
Regarding claim 10, Sato ‘004 discloses
The multilayer electronic component of claim 1, wherein the body includes a capacitance formation portion (where 11 and 21 overlap – figs. 10-11; Note that an instance when the VL layer is insulating, a capacitance will be formed) in which the first and second internal electrodes are disposed alternately in the first direction with the dielectric layer therebetween, and cover portions disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (topmost VL layer and/or bottommost VL layer – fig. 10), wherein the first and second external electrodes are disposed on the second surface (5, 6 – fig. 10), and are not disposed on the first surface (para. [0062]), and wherein the multilayer electronic component further includes a first connection electrode penetrating the cover portion and connecting the first internal electrode disposed in an outermost region with respect to the first direction to the first external electrode (15 and/or 25 – figs. 10-11; para. [0063]), and a second connection electrode penetrating the cover portion and connecting the second internal electrode disposed in an outermost region with respect to the first direction to the second external electrode (55 and/or 65 – figs. 5-6; paras. [0063]).
Regarding claim 11, Sato ‘004 discloses
The multilayer electronic component of claim 1, wherein the body includes a capacitance formation portion (where 11 and 21 overlap – figs. 5-6; Note that an instance when the VL layer is insulating, a capacitance will be formed) in which the first and second internal electrodes are disposed alternately in the first direction with the dielectric layer therebetween, and cover portions disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (topmost VL layer and/or bottommost VL layer – fig. 5), wherein the first and second external electrodes are disposed on the first surface and the second surface, respectively (fig. 5), wherein the first and second external electrodes disposed on the first surface are spaced apart from the first and second external electrodes disposed on the second surface (fig. 5), and wherein the multilayer electronic component further includes a first connection electrode penetrating the cover portion and connecting the first internal electrode disposed in an outermost region with respect to the first direction to the first external electrode (15 and/or 25 – figs. 5-6; para. [0049]), and a second connection electrode penetrating the cover portion and connecting the second internal electrode disposed in an outermost region with respect to the first direction to the second external electrode (55 and/or 65 – figs. 5-6; paras. [0049]).
Regarding claim 12, Sato ‘004 discloses
A multilayer electronic component, comprising: a body (1- fig. 4; para. [0037]) including a first surface and a second surface opposing each other in a first direction (S1, S2, Z – fig. 5), a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction (left, right, X – fig. 5), and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposing each other in a third direction (left, right, Y – figs. 6), and including a first internal electrode layer including a first dielectric layer (VL – fig. 5; para. [0017-0018]), and a first internal electrode (11 – fig. 5) and a first auxiliary electrode (41 – fig. 5) spaced apart from each other in the second direction on the first dielectric layer (fig. 5), and a second internal electrode layer including a second dielectric layer (VL – fig. 5; para. [0017-0018]), and a second internal electrode (21 – fig. 5) and a second auxiliary electrode (31 – fig. 5) spaced apart from each other in the second direction on the second dielectric layer (fig. 5), wherein the first internal electrode layer and the second internal electrode layer are disposed alternately in the first direction (fig. 5); first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively (first: 5 and/or 7, second: 6 and/or 8 – figs. 4-6 or figs. 9-11); a first via electrode penetrating the first dielectric layer and connecting the first internal electrode to the second auxiliary electrode (13a – fig. 5; para. [0049]); a second via electrode penetrating the first dielectric layer and connecting the first auxiliary electrode to the second internal electrode (23b – fig. 5; para. [0049]); a third via electrode penetrating the second dielectric layer and connecting the second auxiliary electrode to the first internal electrode (13b – fig. 5; para. [0049]); and a fourth via electrode penetrating the second dielectric layer and connecting the second internal electrode to the first auxiliary electrode (23a – fig. 5; para. [0049]), wherein the first via electrode is shifted from the third via electrode adjacent thereto in the first direction, and the second via electrode is shifted from the fourth via electrode adjacent thereto in the first direction (fig 5; para. [0049]).
Regarding claim 13, Sato ‘004 discloses
The multilayer electronic component of claim 12, wherein the first via electrode does not overlap the third via electrode (fig. 5), adjacent thereto in the first direction, in the first direction, and wherein the second via electrode does not overlap the fourth via electrode, adjacent in the first direction, in the first direction (fig. 5).
Regarding claim 14, Sato ‘004 discloses
The multilayer electronic component of claim 12, wherein the first via electrode includes a plurality of first via electrodes (fig. 6 shows a plurality of 13a) and the second via electrode includes a plurality of the second via electrodes, penetrating same first dielectric layer (the other side of fig. 6 similarly has a plurality of 23b; para. [0051]), and wherein the third via electrode includes a plurality of the third via electrodes (fig. 6 shows a plurality of 13a) and the fourth via electrode includes a plurality of the fourth via electrodes, penetrating same second dielectric layer (the other side of fig. 6 similarly has a plurality of 23a; para. [0051]).
Regarding claim 15, Sato ‘004 discloses
The multilayer electronic component of claim 14, wherein the plurality of first and second via electrodes penetrating the same first dielectric layer are arranged in the second and third directions, respectively (figs. 5-6), and wherein the plurality of third and fourth via electrodes penetrating the same second dielectric layer are arranged in the second and third directions, respectively (figs. 5-6).
Regarding claim 21, Sato ‘004 discloses
The multilayer electronic component of claim 12, wherein the body includes a capacitance formation portion (where 11 and 21 overlap – figs. 10-11; Note that an instance when the VL layer is insulating, a capacitance will be formed) in which the first and second internal electrodes are alternately disposed with the first dielectric layer or the second dielectric layer therebetween, and cover portions disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (topmost VL layer and/or bottommost VL layer – fig. 10), wherein the first and second external electrodes are disposed on the second surface, and are not disposed on the first surface (figs. 9-11; para. [0062]), and wherein the multilayer electronic component further includes a first connection structure penetrating the cover portion and connecting the first internal electrode or the second auxiliary electrode disposed in an outermost region with respect to the first direction to the first external electrode (15 and/or 25 – figs. 10-11; para. [0063]), and a second connection structure penetrating the cover portion and connecting the second internal electrode or the first auxiliary electrode disposed in an outermost region with respect to the first direction to the second external electrode (55 and/or 65 – figs. 10-11; para. [0063]).
Regarding claim 22, Sato ‘004 discloses
The multilayer electronic component of claim 12, wherein the body includes a capacitance formation portion (where 11 and 21 overlap – figs. 5-6; Note that an instance when the VL layer is insulating, a capacitance will be formed) in which the first and second internal electrodes are alternately disposed with the first dielectric layer or the second dielectric layer therebetween, and cover portions disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (topmost VL layer and/or bottommost VL layer – fig. 5), wherein the first and second external electrodes are disposed on the first surface and the second surface, respectively (fig. 5), wherein the first and second external electrodes disposed on the first surface are spaced apart from the first and second external electrodes disposed on the second surface (figs. 4-6; para. [0038-0039]), wherein the multilayer electronic component further includes a first connection structure penetrating the cover portion and connecting the first internal electrode or the second auxiliary electrode disposed in an outermost region with respect to the first direction to the first external electrode (15 and/or 25 – figs. 5-6; para. [0049]), and a second connection structure penetrating the cover portion and connecting the second internal electrode or the first auxiliary electrode disposed in an outermost region with respect to the first direction to the second external electrode (55 and/or 65 – figs. 5-6; paras. [0049]).
Claim(s) 28-33 and 36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakaguchi JP 2009177054 A.
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Figure 3: Examiner annotated fig. 1 of Sakaguchi ‘054 showing a capacitance forming portion, a first margin region, a second margin region, and L, T, W directions.
Regarding claim 28, Sakaguchi ‘054 discloses
A multilayer electronic component, comprising: a body (53 – fig. 1; para. [0010]) including: a capacitance forming portion (capacitance forming portion – present office action figure 3, hereafter called POA3) comprising: first internal electrodes extending in a length-width plane (leftmost 50, L-W – POA3; para. [0010]), second internal electrodes extending in the length-width plane (rightmost 50, L-W – POA3; para. [0010]) and overlapping the first internal electrodes in a thickness direction (T – POA3), and dielectric layers disposed between the first and second internal electrodes adjacent to each other (52 – fig. 1; para. [0010]); and a margin portion (first margin portion, second margin portion – POA3) comprising: a first margin region (first margin region – POA3) wherein the dielectric layers are disposed between the first internal electrodes in the thickness direction without having second internal electrodes disposed between, and a second margin region (second margin region – POA3) wherein the dielectric layers are disposed between the second internal electrodes in the thickness direction without having first internal electrodes disposed therebetween; and first via electrodes (leftmost 51 inside of the first margin region – POA3) extending in the thickness direction and disposed in the first margin region, connecting adjacent first internal electrodes in the thickness direction (POA3 and para. [0010]).
Regarding claim 29, Sakaguchi ‘054 discloses
The multilayer electronic component of claim 28, further comprising second via electrodes (rightmost 51 inside of the second margin region – POA3) extending in the thickness direction and disposed in the second margin region, connecting adjacent second internal electrodes in the thickness direction (POA3 and para. [0010]).
Regarding claim 30, Sakaguchi ‘054 discloses
The multilayer electronic component of claim 28, further comprising a first external electrode (leftmost 54 – fig. 1; para. [0010]) connected to the first internal electrodes (fig. 1 and para. [0010] shows the first external electrode connected to the first internal electrodes by vias) and a second external electrode (rightmost 54 – fig. 1; para. [0010]) connected to the second internal electrodes (fig. 1 and para. [0010] shows the second external electrode connected to the second internal electrodes by vias).
Regarding claim 31, Sakaguchi ‘054 discloses
The multilayer electronic component of claim 30, further comprising cover portions comprising at least one dielectric layer and covering the capacitance forming region in the thickness direction (top and bottom of POA3 clearly shows a dielectric layer covering the capacitance forming region).
Regarding claim 32, Sakaguchi ‘054 discloses
The multilayer electronic component of claim 31, further comprising first connection vias (leftmost 51 outside of the first margin region – POA3) penetrating the cover portions in the thickness direction and connecting a portion of the first external electrode to the first internal electrodes (POA3), and second connection vias (rightmost 51 outside of the second margin region – POA3) penetrating the cover portions in the thickness direction and connecting a portion of the second external electrode to the second internal electrodes (POA3).
Regarding claim 33, Sakaguchi ‘054 discloses
The multilayer electronic component of claim 31, wherein the body further comprises the cover portions (53 – fig. 1 shows that the body includes the cover portions).
Regarding claim 36, Sakaguchi ‘054 discloses
The multilayer electronic component of claim 33, wherein the first and second external electrodes are disposed on a length-width surface of the body (POA3 and para. [0010]).
Claim(s) 28, 30-31, and 33-37 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. KR 20160071610 A.
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Figure 4: Examiner annotated fig. 1 of Lee ‘610 showing a capacitance forming portion, a first margin region, a second margin region, and L, T, W directions
Regarding claim 28, Lee ‘610 discloses
A multilayer electronic component, comprising: a body (110 – fig. 1; para. [0017]) including: a capacitance forming portion (capacitance forming portion – present office action figure 4, hereafter called POA4) comprising: first internal electrodes extending in a length-width plane (121, L-W – POA4 para. [0024]), second internal electrodes extending in the length-width plane and overlapping the first internal electrodes in a thickness direction (121, T – POA4; para. [0024]), and dielectric layers disposed between the first and second internal electrodes adjacent to each other (111 – fig. 1; para. [0021]); and a margin portion (first margin portion and second margin portion – POA4) comprising: a first margin region (first margin region – POA4) wherein the dielectric layers are disposed between the first internal electrodes in the thickness direction without having second internal electrodes disposed between (POA4), and a second margin region (second margin region – POA4) wherein the dielectric layers are disposed between the second internal electrodes in the thickness direction without having first internal electrodes disposed therebetween (POA4); and first via electrodes (leftmost 140 – POA4; para. [0026]) extending in the thickness direction and disposed in the first margin region (POA4), connecting adjacent first internal electrodes in the thickness direction (POA4 and para. [0026]).
Regarding claim 30, Lee ’610 discloses
The multilayer electronic component of claim 28, further comprising a first external electrode (151 – fig. 1) connected to the first internal electrodes (para. [0042]) and a second external electrode (152 – fig. 1) connected to the second internal electrodes (para. [0042]).
Regarding claim 31, Lee ’610 discloses
The multilayer electronic component of claim 30, further comprising cover portions comprising at least one dielectric layer and covering the capacitance forming region in the thickness direction (161, 162 – POA4 and para. [0004]).
Regarding claim 33, Lee ‘610 discloses
The multilayer electronic component of claim 31, wherein the body further comprises the cover portions (POA4 shows the cover portions as part of the body).
Regarding claim 34, Lee ‘610 discloses
The multilayer electronic component of claim 33, wherein the first and second external electrodes are disposed on opposing thickness-width surfaces of the body (POA4).
Regarding claim 35, Lee ‘610 discloses
The multilayer electronic component of claim 34, wherein the first and second external electrodes extend at least to opposing length-width surfaces of the body while being spaced apart from each other (POA4).
Regarding claim 36, Lee ‘610 discloses
The multilayer electronic component of claim 33, wherein the first and second external electrodes are disposed on a length-width surface of the body (POA4).
Regarding claim 37, Lee ‘610 discloses
The multilayer electronic component of claim 28, wherein the margin portion further comprises second auxiliary electrodes (131 – POA4) disposed in the first margin region, spaced apart from the second internal electrodes and in a same plane as a corresponding second internal electrode among the second internal electrodes (POA4), and wherein the first via electrodes connect the first internal electrodes with adjacent second auxiliary electrodes in the thickness direction (POA4 and para. [0024]).
Claim(s) 1, 3-5, and 12-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tani US 20090310278 A1.
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Figure 5: Examiner annotated fig. 6 of Tani ‘278 showing directions.
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Figure 6: Examiner annotated fig. 7 of Tani ‘278 showing a plurality of first via electrodes and a plurality of third via electrodes.
Regarding claim 1, Tani ‘278 discloses
A multilayer electronic component, comprising: a body (10 – fig. 2; para. [0084]) including a dielectric layer (50 – fig. 2; para. [0087]) and first and second internal electrodes disposed alternately in a first direction with the dielectric layer therebetween (41, 42 – fig. 2; para. [0086]), and including a first surface and a second surface opposing each other in the first direction (11, 12, up direction – fig. 2), a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction (21, 22, right direction – fig. 2), and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposing each other in a third direction (31, 32 – fig. 1; out of page direction – fig. 2); first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively (1, 2 – fig. 2; para. [0051]); first via electrodes penetrating the dielectric layer and connecting two first internal electrodes adjacent to each other in the first direction (41d – fig. 4; para. [0058] discloses that the connection portions 41d are disposed in recesses and therefore penetrate the first dielectric layer); and second via electrodes penetrating the dielectric layer and connecting two second internal electrodes adjacent to each other in the first direction (41d – fig. 4; para. [0058] discloses that the connection portions 41d are disposed in recesses and therefore penetrate the first dielectric layer. Furthermore, para. [0053] discloses that side 22 has a structure like side 21), wherein two first via electrodes adjacent to each other in the first direction are shifted from each other, and two second via electrodes adjacent to each other in the first direction are shifted from each other (fig. 4 shows adjacent vias 41d shifted from one another and not overlapping in the first direction. Furthermore, para. [0053] discloses that side 22 has a structure like side 21).
Regarding claim 3, Tani ‘278 discloses
The multilayer electronic component of claim 1, wherein a plurality of first via electrodes and a plurality of second via electrodes, penetrating a same dielectric layer, are provided (fig. 4 and para. [0053]).
Regarding claim 4, Tani ‘278 discloses
The multilayer electronic component of claim 3, wherein the plurality of first and second via electrodes penetrating the same dielectric layer are arranged in the second and third directions (Since the plurality of first and second via electrodes are three-dimensional, they are arranged in the second and third directions).
Regarding claim 5, Tani ‘278 discloses
The multilayer electronic component of claim 1, wherein the first internal electrode is connected to the first external electrode on the third surface, and wherein the second internal electrode is connected to the second external electrode on the fourth surface (fig. 2 and para. [0029]).
Regarding claim 12, Tani ‘278 discloses
A multilayer electronic component, comprising: a body (10 – fig. 6; para. [0084]) including a first surface and a second surface opposing each other in a first direction (11, 12, T – present office action figure 5, hereafter called POA5), a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction (21, 22, L – POA5), and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposing each other in a third direction (31, 32, W – fig. 1 and POA5), and including a first internal electrode layer (layer made up of 50, 41, and D2 – fig. 6) including a first dielectric layer (50 – fig. 6), and a first internal electrode (41 –fig. 6) and a first auxiliary electrode (D2 – fig. 6) spaced apart from each other in the second direction on the first dielectric layer (POA5 and para. [0086]), and a second internal electrode layer (layer made up of 50, 42, and D1 – fig. 6) including a second dielectric layer (50 – fig. 6), and a second internal electrode (42 – fig. 6) and a second auxiliary electrode (D1 – fig. 6) spaced apart from each other in the second direction on the second dielectric layer (POA5 and para. [0086]), wherein the first internal electrode layer and the second internal electrode layer are disposed alternately in the first direction (POA5); first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively (1, 2 – fig. 6; para. [0051]); a first via electrode penetrating the first dielectric layer and connecting the first internal electrode to the second auxiliary electrode (first via electrode – present office action figure 6, hereafter called POA6. Para. [0058] discloses that the connection portions 41d are disposed in recesses and therefore penetrate the first dielectric layer); a second via electrode penetrating the first dielectric layer and connecting the first auxiliary electrode to the second internal electrode (POA6; para. [0058] discloses that the connection portions 41d are disposed in recesses and therefore penetrate the first dielectric layer. Furthermore, para. [0087] discloses that side 22 has a structure like side 21); a third via electrode penetrating the second dielectric layer and connecting the second auxiliary electrode to the first internal electrode (third via electrode – POA6. Para. [0058] discloses that the connection portions 41d are disposed in recesses and therefore penetrate the first dielectric layer); and a fourth via electrode penetrating the second dielectric layer and connecting the second internal electrode to the first auxiliary electrode (Para. [0058] discloses that the connection portions 41d are disposed in recesses and therefore penetrate the first dielectric layer. Furthermore, para. [0087] discloses that side 22 has a structure like side 21), wherein the first via electrode is shifted from the third via electrode adjacent thereto in the first direction, and the second via electrode is shifted from the fourth via electrode adjacent thereto in the first direction (fig. 7 shows vias 41d shifted from one another. Para. [0087] discloses that side 22 has a structure like side 21).
Regarding claim 13, Tani ‘278 discloses
The multilayer electronic component of claim 12, wherein the first via electrode does not overlap the third via electrode, adjacent thereto in the first direction, in the first direction, and wherein the second via electrode does not overlap the fourth via electrode, adjacent in the first direction, in the first direction (POA6 shows vias 41d shifted from one another and not overlapping in a first direction. Furthermore, para. [0087] discloses that side 22 has a structure like side 21).
Regarding claim 14, Tani ‘278 discloses
The multilayer electronic component of claim 12, wherein the first via electrode includes a plurality of first via electrodes and the second via electrode includes a plurality of the second via electrodes, penetrating same first dielectric layer, and wherein the third via electrode includes a plurality of the third via electrodes and the fourth via electrode includes a plurality of the fourth via electrodes, penetrating same second dielectric layer (POA6 shows a plurality of first and third via electrodes. Furthermore, para. [0087] discloses that side 22 has a structure like side 21).
Regarding claim 15, Tani ‘278 discloses
The multilayer electronic component of claim 14, wherein the plurality of first and second via electrodes penetrating the same first dielectric layer are arranged in the second and third directions, respectively (Since the plurality of first and second via electrodes are three-dimensional, they are arranged in the second and third directions), and wherein the plurality of third and fourth via electrodes penetrating the same second dielectric layer are arranged in the second and third directions, respectively (Since the plurality of third and fourth via electrodes are three-dimensional, they are arranged in the second and third directions).
Regarding claim 16, Tani ‘278 discloses
The multilayer electronic component of claim 15, wherein the first dielectric layer includes a first region disposed between two first via electrodes adjacent to each other in the second or third direction among the plurality of first via electrodes (first region – POA6), and a second region disposed between two second via electrodes adjacent to each other in the second or third direction among the plurality of second via electrodes (a second region is formed like the first region according to para. [0087]), wherein the plurality of third via electrodes overlap the first region in the first direction (POA6 shows the third via electrodes overlapping the first region in the same manner as fig. 23 of the applicant’s present disclosure), and wherein the plurality of fourth via electrodes overlap the second region in the first direction (para. [0087] discloses that side 22 has a structure like side 21).
Regarding claim 17, Tani ‘278 discloses
The multilayer electronic component of claim 12, wherein the first internal electrode is connected to the first external electrode on the third surface (fig. 6 and para. [0029]), and wherein the second internal electrode is connected to the second external electrode on the fourth surface (fig. 6 and para. [0029]).
Regarding claim 18, Tani ‘278 discloses
The multilayer electronic component of claim 12, wherein the first auxiliary electrode is connected to the second external electrode at the fourth surface (fig. 6 and para. [0029]), and wherein the second auxiliary electrode is connected to the first external electrode on the third surface (fig. 6 and para. [0029]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tani US 2009/0310278 A1 in view of Lee et al. US 2015/0021080 A1.
Regarding claim 9, Tani ‘278 discloses
The multilayer electronic component of claim 1, wherein the body includes a capacitance formation portion (fig. 2 where 41 and 42 overlap in the first direction) in which the first and second internal electrodes are disposed alternately in the first direction with the dielectric layer therebetween (fig. 2), and cover portions disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (dielectric layer 50 disposed on top and bottom of fig. 2), wherein the first external electrode is disposed on the third surface and extends to a portion of the first surface and the second surface (1 – fig. 2), wherein the second external electrode is disposed on the fourth surface and extends to a portion of the first surface and the second surface (2 – fig. 2). Tani ‘278 fails to disclose wherein the multilayer electronic component further includes a first connection electrode penetrating the cover portions and connecting the first internal electrode disposed in an outermost region thereof in the first direction to the first external electrode, and a second connection electrode penetrating the cover portions and connecting the second internal electrode disposed in an outermost region thereof in the first direction to the second external electrode.
Lee ‘080 discloses wherein the multilayer electronic component further includes a first connection electrode (21a – fig. 2) penetrating the cover portions and connecting the first internal electrode disposed in an outermost region thereof in the first direction to the first external electrode (para. [0018]), and a second connection electrode (22a – fig. 2) penetrating the cover portions and connecting the second internal electrode disposed in an outermost region thereof in the first direction to the second external electrode (para. [0018]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Tani ‘278 to include a first connection electrode penetrating the cover portions and connecting the first internal electrode disposed in an outermost region thereof in the first direction to the first external electrode, and a second connection electrode penetrating the cover portions and connecting the second internal electrode disposed in an outermost region thereof in the first direction to the second external electrode as taught by Lee ‘080 in order to reduce equivalent series inductance (ESL) by shortening a current path (para. [0090-0096] of Lee ‘080).
Regarding claim 20, Tani ‘278 discloses
The multilayer electronic component of claim 12, wherein the body includes a capacitance formation portion (fig. 6 where 41 and 42 overlap in the first direction) in which the first and second internal electrodes are alternately disposed with the first dielectric layer or the second dielectric layer therebetween (fig. 6), and cover portions disposed on both surfaces of the capacitance formation portion opposing each other in the first direction (dielectric layer 50 disposed on top and bottom of fig. 6), wherein the first external electrode is disposed on the third surface and extends to a portion of the first surface and second surface (1 – fig. 6), wherein the second external electrode is disposed on the fourth surface and extends to a portion of the first surface and second surface (2 – fig. 6). Tani ‘278 fails to discloses wherein the multilayer electronic component further includes a first connection structure penetrating the cover portion and connecting the first internal electrode or the second auxiliary electrode disposed in an outermost region with respect to the first direction to the first external electrode, and a second connection structure penetrating the cover portion and connecting the second internal electrode or the first auxiliary electrode disposed in an outermost region with respect to the first direction to the second external electrode.
Lee ‘080 discloses wherein the multilayer electronic component further includes a first connection structure (21a – fig. 2) penetrating the cover portion and connecting the first internal electrode or the second auxiliary electrode disposed in an outermost region with respect to the first direction to the first external electrode (para. [0018]), and a second connection structure (22a – fig. 2) penetrating the cover portion and connecting the second internal electrode or the first auxiliary electrode disposed in an outermost region with respect to the first direction to the second external electrode (para. [0018]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Tani ‘278 to include wherein the multilayer electronic component further includes a first connection structure penetrating the cover portion and connecting the first internal electrode or the second auxiliary electrode disposed in an outermost region with respect to the first direction to the first external electrode, and a second connection structure penetrating the cover portion and connecting the second internal electrode or the first auxiliary electrode disposed in an outermost region with respect to the first direction to the second external electrode as taught by Lee ‘080 in order to reduce equivalent series inductance (ESL) by shortening a current path (para. [0090-0096] of Lee ‘080).
Claim(s) 12 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujimura et al. JP 2013161983 A in view of Kim et al. US 2016/0233024 A1.
Regarding claim 12, Fujimura ‘983 discloses
A multilayer electronic component, comprising: a body (4 – fig. 1; para. [0020]) including a first surface and a second surface opposing each other in a first direction (top, bottom, Z – fig. 1), a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction (left, right, X – fig. 1), and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposing each other in a third direction (front, back, Y – fig. 1), and including a first internal electrode layer including a first dielectric layer (10 – fig. 1; para. [0020]), and a first internal electrode (12 – fig. 1; para. [0020]) and a first auxiliary electrode spaced apart from each other in the second direction on the first dielectric layer, and a second internal electrode layer including a second dielectric layer (10 – fig. 1; para. [0020]), and a second internal electrode (13 – fig. 1; para. [0020]) and a second auxiliary electrode spaced apart from each other in the second direction on the second dielectric layer, wherein the first internal electrode layer and the second internal electrode layer are disposed alternately in the first direction (fig. 1); first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively (6, 8 – fig. 1; para. [0020]); a first via electrode penetrating the first dielectric layer (24 – fig. 1; para. [0036] discloses 24 is also formed on the left side of the body); a second via electrode penetrating the first dielectric layer (24 – fig. 1; para. [0026]); a third via electrode penetrating the second dielectric layer (24 – fig. 1; para. [0036] discloses 24 is also formed on the left side of the body); and a fourth via electrode penetrating the second dielectric layer (24 – fig. 1; para. [0026]), wherein the first via electrode is shifted from the third via electrode adjacent thereto in the first direction, and the second via electrode is shifted from the fourth via electrode adjacent thereto in the first direction (Fig. 1 shows vias (24) shifted from one another. Furthermore, para. [0058] discloses that the vias are randomly formed. Therefore, the vias will be shifted from one another.). Fujimura ‘983 fails to disclose a first internal electrode layer including a first internal electrode and a first auxiliary electrode spaced apart from each other in the second direction on the first dielectric layer, and a second internal electrode layer including a second internal electrode and a second auxiliary electrode spaced apart from each other in the second direction on the second dielectric layer; a first via electrode connecting the first internal electrode to the second auxiliary electrode; a second via electrode connecting the first auxiliary electrode to the second internal electrode; a third via electrode connecting the second auxiliary electrode to the first internal electrode; and a fourth via electrode connecting the second internal electrode to the first auxiliary electrode.
Kim ‘024 discloses a first internal electrode layer including a first internal electrode and a first auxiliary electrode (23 – fig. 2) spaced apart from each other in the second direction on the first dielectric layer (para. [0044]), and a second internal electrode layer including a second internal electrode and a second auxiliary electrode (24 – fig. 2) spaced apart from each other in the second direction on the second dielectric layer (para. [0044]). As the vias (24) are randomly formed (para. [0058]), after modification of Fujimura ‘983 with Kim ‘024 the following structure will be present: a first via electrode connecting the first internal electrode to the second auxiliary electrode; a second via electrode connecting the first auxiliary electrode to the second internal electrode; a third via electrode connecting the second auxiliary electrode to the first internal electrode; and a fourth via electrode connecting the second internal electrode to the first auxiliary electrode.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Fujimura ‘983 to include a first internal electrode layer including a first internal electrode and a first auxiliary electrode spaced apart from each other in the second direction on the first dielectric layer, and a second internal electrode layer including a second internal electrode and a second auxiliary electrode spaced apart from each other in the second direction on the second dielectric layer as taught by Kim ’024 in order to improve a step difference, which prevents tilting or tombstoning when mounting the capacitor (paras. [0039-0041] and [0047] of Kim ‘024).
Regarding claim 14, modified Fujimura ‘983 discloses
The multilayer electronic component of claim 12, wherein the first via electrode includes a plurality of first via electrodes and the second via electrode includes a plurality of the second via electrodes, penetrating same first dielectric layer (fig. 1 and paras. [0036] and [0058] disclose that multiple vias (24) penetrate a dielectric layer), and wherein the third via electrode includes a plurality of the third via electrodes and the fourth via electrode includes a plurality of the fourth via electrodes, penetrating same second dielectric layer (fig. 1 and para. [0058] disclose that multiple vias (24) penetrate a dielectric layer).
Regarding claim 15, modified Fujimura ‘983 discloses
The multilayer electronic component of claim 14, wherein the plurality of first and second via electrodes penetrating the same first dielectric layer are arranged in the second and third directions respectively (Paras. [0036] and [0058] discloses the vias (24) are randomly formed and therefore may be arranged in the second and third directions. Furthermore, the vias have a three-dimensional shape and will therefore be arranged in the second and third directions), and wherein the plurality of third and fourth via electrodes penetrating the same second dielectric layer are arranged in the second and third directions, respectively (Para. [0058] discloses the vias (24) are randomly formed and therefore may be arranged in the second and third directions. Furthermore, the vias have a three-dimensional shape and will therefore be arranged in the second and third directions).
Regarding claim 16, modified Fujimura discloses
The multilayer electronic component of claim 15, wherein the first dielectric layer includes a first region disposed between two first via electrodes adjacent to each other in the second or third direction among the plurality of first via electrodes (fig. 1 shows a via (24) between two vias above it. Para. [0036] discloses that vias are also formed on the left side of the body in fig .1. Furthermore, para. [0058] discloses that the vias are randomly formed and hence there will be vias overlapping a region between vias on the second or third directions), and a second region disposed between two second via electrodes adjacent to each other in the second or third direction among the plurality of second via electrodes, wherein the plurality of third via electrodes overlap the first region in the first direction, and wherein the plurality of fourth via electrodes overlap the second region in the first direction (fig. 1 shows a via (24) between two vias above it. Furthermore, para. [0058] discloses that the vias are randomly formed and hence there will be vias overlapping a region between vias on the second or third directions).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. JP 2010041004 A in view of Matsushita JP 2012227207 A.
Regarding claim 19, Sato ‘004 discloses
The multilayer electronic component of claim 12. Sato fails to disclose wherein a width of an upper surface of the first via electrode is greater than a width of a lower surface of the first via electrode, wherein a width of an upper surface of the second via electrode is greater than a width of a lower surface of the second via electrode, wherein a width of an upper surface of the third via electrode is greater than a width of a lower surface of the third via electrode, and wherein a width of an upper surface of the fourth via electrode is greater than a width of a lower surface of the fourth via electrode.
Matsushita ‘207 discloses wherein a width of an upper surface of a via electrode is greater than a width of a lower surface of the via electrode (10a – fig. 4; para. [0052]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the first, second, third and fourth via electrode of Sato ‘004 to have a width of an upper surface of modify the first, second, third and fourth via electrode be greater than a width of a lower surface of modify the first, second, third and fourth via electrode in order to reduce damage to the dielectric layer (para. [0054] of Matsushita ‘207).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20090214881 A1: fig. 2 shows cone shaped vias and auxiliary electrodes
US 20090284897 A1: fig. 13
US 20180277305 A1: fig. 1
US 20100002356 A1: para. [0007] for dummy/auxiliary electrodes
KR 20150051421 A: fig. 2
JP 2012227207 A: fig. 4
US 20060180899 A1: para. [0028]
US-20180027656-A1: Paras. [0077], [0079], [0121] and [0123]
US 2018/0090275 A1: Paras. [0145-0146]
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/T.J.T./Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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