DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
The Examiner called Applicant's representative on 07/22/2026, and left a message. A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b)..
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 7, 10-13, and 15-19 of U.S. Patent No. US 12154207 B2 in view of Yamada et al. (US 20130254592 A1).
Table I:
Mapping of contending claims in the patent that contains double patenting issues.
Current Application (18919846)
Patent (US 12154207 B2) in view of Yamada et al.
21
1
22
2
23
3
24
4
25
5
26
1
27
7
28
10
29
11
30
10, 3
31
12-13
32
10
33
15
34
16
35
17
36
16, 3
37
18
38
19
39
16
40
16, 7
Table II:
Current Application (18919846)
Patent (US 12154207 B2) in view of Yamada et al.
Claim 21, A processor comprising:
a processing resource to perform graphics operations using a plurality of threads; and load store pipeline hardware circuitry coupled to the processing resource to:
receive, from memory fabric, a memory access response to a memory access request issued by a thread of the plurality of threads, the memory access response comprising a memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition;
identify, using the memory dependency token, a scoreboard identifier (SBID) associated with the memory access response;
and return an exception phase of the memory access response to a debug register of the processing resource hosting the thread, the exception phase comprising the SBID and the fault details of the page fault error condition.
return data phases of the memory access response to data registers of the processing resource hosting the thread;
Claim 1, A processor comprising:
processing resources to perform graphics operations using a plurality of threads; and load store pipeline hardware circuitry coupled to the processing resources to:
receive, from the memory fabric in response to the memory access request, a memory access response comprising the memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition; and
in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (SBID) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory access request comprising the memory dependency token;
and return the SBID associated with the memory access response and fault details of the page fault error condition to a debug register of the thread, the thread to utilize the SBID and the fault details to report to a debugger application that associates the page fault error condition to the thread using the SBID.
Yamada,
¶100 reciting “In response to the memory access (read), the read data 61 in the system bus 6 is read by the CPU core 2A at CLKNO=5, and written in a register (for example, a general register) in a register set corresponding to the thread number 1 in the CPU core 2A (period A1-1).”
Claim 21 is rejected for obviousness type double patenting over claim 1 of the patent 12154207 in view of Yamada for having similar limitations as described in Table 2.
The patent 12154207 fails to disclose limitation “return data phases of the memory access response to data registers of the processing resource hosting the thread” in Claim 21.
It is well known in the art to return data of the memory access response to a data register of the processing resource hosting the thread. In addition, Yamada teaches “When the CPU core 2A executes a memory access (read) at CLKNO=4, the command 60 and the address 60 are output to the system bus 6 via the system bus control circuit 5 (period A1-1). In response to the memory access (read), the read data 61 in the system bus 6 is read by the CPU core 2A at CLKNO=5, and written in a register (for example, a general register) in a register set corresponding to the thread number 1 in the CPU core 2A (period A1-1).” (¶100)
It would have been obvious to one with ordinary skill, before the effective filing date of the claimed invention, to combine the teachings from patent 12154207 and Yamada to return data phases of the memory access response to data registers of the processing resource hosting the thread. The suggestions/motivations would have been to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results.
Although the conflicting claims are not identical, they are not patentably distinct from each other because the scope of the inventions is the same. Claim 21 of current application is an obvious variant of claim 1 of the patent 12154207 in view of Yamada.
The same logic applies to Claims 22-40. They are rejected for obviousness type double patenting under claims 1-5, 7, 10-13, and 15-19 of the patent 12154207 in view of Yamada.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YI WANG whose telephone number is (571)272-6022. The examiner can normally be reached 9am - 5pm.
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/YI WANG/Primary Examiner, Art Unit 2619
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