DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to Response to Election/Restriction for application 18919947 filed on 06/18/2026. Claims 1, 3-21 are presented for examination, of which claims 17-20 are withdrawn from consideration.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12154515. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application would have been obvious to a person ordinary skill in the art before the time of the first effective filing of the claimed invention in light of claim 3 of U.S. Patent No. 12154515, see table below for more detail comparison with same/similar limitations bolded, and what is not explicitly taught italicized.
Claim 1 of Instant Application
Claim 3 of U.S. Patent No. 12154515
1. A method of operating a display pixel, comprising:
with an emission transistor, selectively passing current from a drive transistor to a light-emitting diode;
with a first capacitor coupled between a gate terminal of the drive transistor and an anode terminal of the light-emitting diode, storing a data signal for the display pixel;
with a second capacitor coupled to a source-drain terminal of the drive transistor, receiving an adjustable voltage signal;
and with a data loading transistor coupled to the source-drain terminal of the drive transistor, receiving the adjustable voltage signal or a scan control signal separate from the adjustable voltage signal.
1. A display pixel comprising:
a light-emitting diode;
a drive transistor coupled in series with the light-emitting diode;
a first capacitor having a first terminal coupled to a gate terminal of the drive transistor and having a second terminal coupled to an anode of the light-emitting diode;
a second capacitor having a first terminal coupled to a source terminal of the drive transistor and having a second terminal configured to receive an adjustable voltage signal; and
a data loading transistor coupled to the source terminal of the drive transistor and configured to receive the adjustable voltage signal or a scan control signal separate from the adjustable voltage signal.
2. The display pixel of claim 1, further comprising:
a first gate driver having an output coupled to a gate terminal of the data loading transistor; and
a second gate driver having an output coupled to the second terminal of the second capacitor.
3. The display pixel of claim 2, further comprising:
a first emission transistor coupled between a power supply line and a drain terminal of the drive transistor;
a second emission transistor coupled between the source terminal of the drive transistor and the anode of the light-emitting diode;
a gate-to-drain transistor coupled between the drain terminal and the gate terminal of the drive transistor; and
an initialization transistor having a first terminal coupled to the anode of the light-emitting diode and a second terminal coupled to an initialization line.
It can be seen from the table above that claim 3 of U.S. Patent No. 12154515 teaches most of the limitations of claim 1 of the instant application with one of the exceptions that claim 3 of U.S. Patent No. 12154515 is directed to a display pixel (apparatus claim), wherein claim 1 of the instant application is directed to a method of operating a display pixel (method claim). However, the steps of the method are mostly inherent functionalities of the apparatus elements, hence would have been obvious to a person ordinary skill in the art before the time of the first effective filing of the claimed invention.
Another difference of claim 3 of U.S. Patent No. 12154515 and claim 1 of the instant application is that claim 3 of U.S. Patent No. 12154515 does not explicitly recite the first capacitor storing a data signal for the display pixel. However, since it has been well-known that data signals are feed to the gate terminal of the drive transistor of a pixel circuit and that the controlling of the amount of current passing through a drive transistor is the difference between gate and source of said transistor, which is where the first capacitor is coupled to, it would have been obvious that the first capacitor that is coupled between the drive transistor gate terminal and the light-emitting diode anode terminal would/could be storing a data signal for the display pixel.
Allowable Subject Matter
Claim 1 would be allowable the above double-patenting rejection would be resolved.
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-16 and 21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the data loading transistor connected to the same source-drain terminal of the driver transistor where the adjustable voltage signal, scan control signal or control voltage is applied in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Response to Arguments
Regarding the double-patenting rejection, even with the added limitations to claim 1, it still appears that claim 3 of U.S. Patent No. 12154515, see comparison table above with the newly amended portion of claim 1 underlined and the corresponding limitation in claim 3 is also underlined. In light of that, the double-rejection is maintained.
Regarding the potential rejoinder of claims 17-20, since claim 1 is still rejected over double-patenting, but would potentially be rejoined if the double-patenting of claim 1 is resolved.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG HUI LIANG whose telephone number is (571)272-0487. The examiner can normally be reached M-F 7am-3pm EST.
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/DONG HUI LIANG/Primary Examiner, Art Unit 2629
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