DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to Response to Election/Restriction for application 18919947 filed on 02/26/2026. Claims 1-20 are presented for examination, of which claims 17-20 are withdrawn from consideration.
Election/Restrictions
Applicant’s election without traverse of Species I directed to claims 1-16 in the reply filed on 02/26/2026 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12154515. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application would have been obvious to a person ordinary skill in the art before the time of the first effective filing of the claimed invention in light of claim 3 of U.S. Patent No. 12154515, see table below for more detail comparison with same/similar limitations bolded, and what is not explicitly taught underlined.
Claim 1 of Instant Application
Claim 3 of U.S. Patent No. 12154515
1. A method of operating a display pixel, comprising:
with an emission transistor, selectively passing current from a drive transistor to a light-emitting diode;
with a first capacitor coupled between a gate terminal of the drive transistor and an anode terminal of the light-emitting diode, storing a data signal for the display pixel;
with a second capacitor coupled to a source-drain terminal of the drive transistor, receiving an adjustable voltage signal;
and with a data loading transistor, receiving the adjustable voltage signal or a scan control signal separate from the adjustable voltage signal.
1. A display pixel comprising:
a light-emitting diode;
a drive transistor coupled in series with the light-emitting diode;
a first capacitor having a first terminal coupled to a gate terminal of the drive transistor and having a second terminal coupled to an anode of the light-emitting diode;
a second capacitor having a first terminal coupled to a source terminal of the drive transistor and having a second terminal configured to receive an adjustable voltage signal; and
a data loading transistor coupled to the source terminal of the drive transistor and configured to receive the adjustable voltage signal or a scan control signal separate from the adjustable voltage signal.
2. The display pixel of claim 1, further comprising:
a first gate driver having an output coupled to a gate terminal of the data loading transistor; and
a second gate driver having an output coupled to the second terminal of the second capacitor.
3. The display pixel of claim 2, further comprising:
a first emission transistor coupled between a power supply line and a drain terminal of the drive transistor;
a second emission transistor coupled between the source terminal of the drive transistor and the anode of the light-emitting diode;
a gate-to-drain transistor coupled between the drain terminal and the gate terminal of the drive transistor; and
an initialization transistor having a first terminal coupled to the anode of the light-emitting diode and a second terminal coupled to an initialization line.
It can be seen from the table above that claim 3 of U.S. Patent No. 12154515 teaches most of the limitations of claim 1 of the instant application with one of the exceptions that claim 3 of U.S. Patent No. 12154515 is directed to a display pixel (apparatus claim), wherein claim 1 of the instant application is directed to a method of operating a display pixel (method claim). However, the steps of the method are mostly inherent functionalities of the apparatus elements, hence would have been obvious to a person ordinary skill in the art before the time of the first effective filing of the claimed invention.
Another difference of claim 3 of U.S. Patent No. 12154515 and claim 1 of the instant application is that claim 3 of U.S. Patent No. 12154515 does not explicitly recite the first capacitor storing a data signal for the display pixel. However, since it has been well-known that data signals are feed to the gate terminal of the drive transistor of a pixel circuit and that the controlling of the amount of current passing through a drive transistor is the difference between gate and source of said transistor, which is where the first capacitor is coupled to, it would have been obvious that the first capacitor that is coupled between the drive transistor gate terminal and the light-emitting diode anode terminal would/could be storing a data signal for the display pixel.
Prior Art Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-8, 15 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ilda et al. (US Patent Pub. No. 2008/0030437 A1)
Regarding claim 1, Iida teaches a method of operating a display pixel (Ilda, Fig. 5, pixel 101), comprising:
with an emission transistor, selectively passing current from a drive transistor to a light-emitting diode (Ilda, Fig. 5, driving transistor 3B, Ilda, [0074]. Drai current of driving transistor 3B Ids to light emitting element 3D);
with a first capacitor coupled between a gate terminal of the drive transistor and an anode terminal of the light-emitting diode, storing a data signal for the display pixel (Ilda, Fig. 5, storage capacitor 3C storing image data from signal line DTL101 via 3A);
with a second capacitor coupled to a source-drain terminal of the drive transistor, receiving an adjustable voltage signal (Ilda, Fig. 5, auxiliary capacitor 3J, receiving voltage from power supply line DSL101; Ilda, Fig. 6, power suppl line potential (DSL101) is adjustable); and
with a data loading transistor, receiving the adjustable voltage signal or a scan control signal separate from the adjustable voltage signal (Ilda, Fig. 5, sampling transistor 3A receives DTL101 and WSL101).
Regarding claim 5, Ilda teaches the limitations of claim 1 and further teaches with a peripheral gate driver, outputting the adjustable voltage signal to the second capacitor and the data loading transistor (Ilda, Fig. 5, the driving units (103, 104 and 105)).
Regarding claim 6, Ilda teaches the limitations of claim 1 and further teaches with a first gate driver, outputting the adjustable voltage signal to the second capacitor Ilda, Fig. 5, power supply scanner (DSCN) 105); and
with a second gate driver different than the first gate driver, outputting the scan control signal to the data loading transistor. (Ilda, Fig. 5, main scanner (write scanner WSCN) 104)
Regarding claim 7, Ilda teaches the limitations of claim 1 and further teaches during a data programming period, using the data loading to load the data signal into the display pixel (Ilda, Figs. 4A and 6, period K); and
concurrent with or subsequent to the data programming period, reducing the adjustable voltage signal (Ilda, Figs. 4A and 6, the cycle is repeated as shown by both light emitting period B and light emitting period L, in the subsequent period after the first K, the same cycle is repeated and DSL101 is changed from VCC_H to VCC_L).
Regarding claim 8, Ilda teaches a method of operating a display pixel (Ilda, Fig. 5, pixel 101), comprising:
with an emission transistor, selectively passing current from a drive transistor to a light-emitting diode (Ilda, Fig. 5, driving transistor 3B, Ilda, [0074]. Drai current of driving transistor 3B Ids to light emitting element 3D);
with a first capacitor coupled between a gate terminal of the drive transistor and an anode terminal of the light-emitting diode, storing a data signal for the display pixel (Ilda, Fig. 5, storage capacitor 3C connected to gate g and source s, which is also anode of light emitting element 3D); and
with a second capacitor coupled to a source-drain terminal of the drive transistor, receiving a control voltage via a row line (Ilda, Fig. 5, auxiliary capacitor 3J, receiving voltage from power supply line DSL101).
Regarding claim 15, Ilda teaches the limitations of claim 8 and further teaches with a data loading transistor, loading the data signal into the display pixel during a data loading period (Ilda, Figs. 4A and 6, period K); and
during or after the data loading period, adjusting the control voltage that is conveyed to the second capacitor from a first voltage level to a second voltage level different than the first voltage level (Ilda, Figs. 4A and 6, the cycle is repeated as shown by both light emitting period B and light emitting period L, in the subsequent period after the first K, the same cycle is repeated and DSL101 is changed from VCC_H to VCC_L).
Regarding claim 16, Ilda teaches the limitations of claim 8 and further teaches with a data loading transistor, loading the data signal into the display pixel during a data loading period (Ilda, Figs. 4A and 6, period K); and
during or after the data loading period, adjusting the control voltage that is conveyed to the second capacitor from a first voltage level to a second voltage level less than the first voltage level (Ilda, Figs. 4A and 6, the cycle is repeated as shown by both light emitting period B and light emitting period L, in the subsequent period after the first K, the same cycle is repeated and DSL101 is changed from VCC_H to VCC_L).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ilda et al. (US Patent Pub. No. 2008/0030437 A1) in view of Yamashita et al. (US Patent Pub. No. 2008/0198104 A1)
Regarding claim 3, Ilda teaches the limitations of claim 1. Ilda does not seem to explicitly teach an additional emission transistor, selectively coupling the drive transistor to a positive power supply line.
However, in a related art of pixel circuit, Yamashita teaches an additional emission transistor, selectively coupling the drive transistor to a positive power supply line (Yamashita, Fig. 2, Tr4).
Before the time of the first effective filing of the claimed invention, it would have been obvious to a person ordinary skill in the art to include the additional emission transistor as suggested by Yamashita in the pixel of Ilda. The suggestion/motivation would have been in order to further reduce leakage current when not emitting light by the pixel (Yamashita, [0018]).
Regarding claim 4, Ilda teaches the limitations of claim 1. Ilda does not seem to explicitly teach an initialization transistor coupled to the first capacitor, applying an initialization voltage to the anode terminal of the light-emitting diode.
However, in a related art of pixel circuit, Yamashita teaches an initialization transistor coupled to the first capacitor, applying an initialization voltage to the anode terminal of the light-emitting diode (Yamashita, Fig. 2, Tr3).
Before the time of the first effective filing of the claimed invention, it would have been obvious to a person ordinary skill in the art to include the initialization transistor as suggested by Yamashita in the pixel of Ilda. The suggestion/motivation would have been in order to precharge/initialize the capacitor to accommodate for the high speed refreshing of larger size screens (Yamashita, [0005] and [0085]).
Allowable Subject Matter
Claims 2 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art, whether considered alone or in combination, fail to disclose the technical features of the claimed invention in context as a whole. Specifically, the data loading transistor connected to the same source-drain terminal of the driver transistor where the adjustable voltage signal, scan control signal or control voltage is applied in the manner claimed as a whole, is not sufficiently taught or suggested in the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG HUI LIANG whose telephone number is (571)272-0487. The examiner can normally be reached M-F 7am-3pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN C. LEE can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DONG HUI LIANG/Primary Examiner, Art Unit 2629