DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 10/18/24. Claims 1-14 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (KR 20230074909 A)
Regarding claim 1. Kim teaches a linear regulator, comprising: a first output stage circuit [130-150], configured to operably generate a first output voltage according to a first control voltage [output of 120];
and a calibration circuit [120], enabled during a first calibration period [after initialization of 110] after the startup of the linear regulator [initial turn on of circuit], wherein during the first calibration period, the calibration circuit is configured to operably generate the first control voltage based on an output-related signal and a reference voltage [Vref], and the output-related signal is related to the first output voltage [page 3 ¶6-¶8];
wherein the first output stage circuit and the calibration circuit form a first control loop [i.e. control loop 140], wherein the first control loop enters an open-loop state after the end of the first calibration period [page 4 ¶3, it is understood circuit enters control loop after calibration since the goal is to calibrate the reference signal Q to better align circuit towards target voltage];
wherein the first output stage circuit includes a second control loop [130], configured to operably regulate the first output voltage in a closed-loop manner [always in close loop] based on the first control voltage and a variation [i.e. vout deviation from Vref] of the first output voltage during an operational period [nominal period after calibration period] following the first calibration period.
Allowable Subject Matter
Claims 2-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838