Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed January 8, 2026 is acknowledged. Claims 15-19 drawn to the non-elected invention(s) have been withdrawn from examination for patentability.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0225114 to Furukawa et al. (“Furukawa”).
With respect to claim 1, Furukawa discloses in Fig. 3 a vertical (e.g., para. 25) power semiconductor device, comprising:
a silicon carbide (e.g., Para. 26) semiconductor body (e.g., 20/43) having a first surface and a second surface opposite to the first surface, the SiC semiconductor body (e.g., 20/43) including a transistor cell area (e.g., 21/43/31) comprising gate structures (e.g., gate 50 shown as separate structures in Fig. 3 is an interconnected gate 50 for 1, 2, and 4 in Fig. 9), a gate pad area (e.g., gate pad 11 in Fig. 1 is connected to gate wiring 12 and gate 50 in Fig. 3 (e.g., Para. 26)), and an interconnection area (e.g., 12) electrically coupling a gate electrode (e.g., 50) of the gate structures and a gate pad (e.g., gate pad 11 in Fig. 1 is connected to gate wiring 12 and gate 50 in Fig. 3 (e.g., Para. 26)) of the gate pad area (e.g., 11 in Fig. 1) via a gate interconnection (e.g., 12);
a sensor electrode (e.g., 13);
a first interlayer dielectric (e.g., the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3) comprising a first interface to the sensor electrode (e.g., 13) and a second interface to the gate electrode (e.g., the rightmost gate 50 in Fig. 3), wherein a value of a conduction band offset at the first interface ranges from 1 eV to 2.5 eV (e.g., as discussed below); and
a second interlayer dielectric (e.g., the second through fourth leftmost insulation film 32 in Fig. 3) comprising a second interface to at least one of the gate electrode (e.g., gate 50 under the same film 32), wherein the second interlayer dielectric (e.g., the second through fourth leftmost insulation film 32 in Fig. 3) laterally adjoins to the first interlayer dielectric (e.g., the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3). As to the feature that a value of a conduction band offset at the first interface (e.g., the surface of the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3 facing 13) ranges from 1 eV to 2.5 eV, such specific parameter will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating the parameters are critical. Absent any evidence demonstrating a patentable difference between the compositions and the criticality of the claimed amounts, the determination of the optimum or workable range(s) given the guidance of the prior art would have been generally prima facie obvious to the skilled artisan. Please see MPEP §2144.05 [R-2](II)(A) and In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) ("[W]here the general conditions of claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."). It is noted that the specification contains no disclosure of either the critical nature of the instant parameters or any unexpected results arising thereof. Since applicant has not established the criticality of the specific parameter, it would have been obvious to one of ordinary skill in the art before the filing of the claimed invention to use this value in the Fig. 3 circuit of Furukawa.
With respect to claim 2, Furukawa in Fig. 3 fails to specifically show sense pad 13 being made of aluminum, copper, titanium, nickel, molybdenum, tungsten, or alloys thereof. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that a pad may be made of aluminum, copper, titanium, nickel, molybdenum, tungsten, or alloys thereof; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement pad 13 in Fig. 3 of Furukawa using the notoriously well-known method of forming a pad using aluminum, copper, titanium, nickel, molybdenum, tungsten, or alloys thereof because the implementation of pad 13 in Fig. 3 of Furukawa requires a specific implementation in fabrication and the notoriously well-known method provides such a specific implementation.
With respect to claim 3, as to the feature that a portion of the first interlayer dielectric at the first interface (e.g., the surface of the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3 facing 13) is made of a high-k material, such specific parameter will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating the parameters are critical. Absent any evidence demonstrating a patentable difference between the compositions and the criticality of the claimed amounts, the determination of the optimum or workable range(s) given the guidance of the prior art would have been generally prima facie obvious to the skilled artisan. Please see MPEP §2144.05 [R-2](II)(A) and In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) ("[W]here the general conditions of claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."). It is noted that the specification contains no disclosure of either the critical nature of the instant parameters or any unexpected results arising thereof. Since applicant has not established the criticality of the specific parameter, it would have been obvious to one of ordinary skill in the art before the filing of the claimed invention to use this value in the Fig. 3 circuit of Furukawa.
With respect to claim 4, the above discussion for claim 3 fails to specifically disclose that the high-k material is an oxide of aluminum, an oxide of zirconium, a nitride of aluminum, an oxide of hafnium, an oxide of yttrium, an oxide of silicon nitride, silicon nitride, or aluminum nitride. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that a high-k material may be made of an oxide of aluminum, an oxide of zirconium, a nitride of aluminum, an oxide of hafnium, an oxide of yttrium, an oxide of silicon nitride, silicon nitride, or aluminum nitride; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the high-k material discussed for claim 3 using the notoriously well-known method of implementing a high-k material using an oxide of aluminum, an oxide of zirconium, a nitride of aluminum, an oxide of hafnium, an oxide of yttrium, an oxide of silicon nitride, silicon nitride, or aluminum nitride because the implementation of the high-k material discussed for claim 3 requires a specific implementation in fabrication and the notoriously well-known method provides such a specific implementation.
With respect to claim 5, the gate structures (e.g., 50 in Fig. 3) comprise a gate dielectric (e.g., gate insulation 30) arranged between the gate electrode (e.g., 50) and the SiC semiconductor body (e.g., 20/43), and a portion of the gate dielectric (e.g., gate insulation 30) at a channel interface to the SiC semiconductor body is a high-k dielectric (e.g., the same discussion for claim 3 similarly applies).
With respect to claim 7, the gate structures (e.g., 50) are planar or trench gate structures (e.g., as shown in Fig. 3), and at least a part of the second interface (e.g., the surface of the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3 facing the rightmost gate 50) is arranged in the transistor cell area (e.g., 21/43/31), the part of the second interface (e.g., the surface of the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3 facing the rightmost gate 50) is arranged in the transistor cell area (e.g., 21/43/31) being directly opposite to the first interface (e.g., the surface of the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3 facing 13) is arranged in the transistor cell area (e.g., 21/43/31).
With respect to claim 8, at least a part of the second interface (e.g., the surface of the second rightmost insulation film 32 in Fig. 3 connecting 13 to the rightmost gate 50 in Fig. 3 facing the rightmost gate 50) is arranged in the interconnection area (e.g., 12), the part of the second interface being directly opposite to the first interface (e.g., as discussed for claim 7).
Allowable Subject Matter
Claims 6 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Lincoln Donovan, can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842