DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to applicant’s communication filed June 5, 2026 in response to PTO Office Action dated May 13, 2026. The applicant’s remarks and amendment to the specification and/or claims were considered with the results that follow.
Claims 1-20 have been presented for examination in this application. In response to the last Office Action, claims 1 and 13 have been amended.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 7-19 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Ravimohan et al. (US# 2016/0202910).
Regarding claim 1, Ravimohan et al. teaches a storage device, comprising: a non-volatile memory (NVM) partitioned into a first set of memory and a second set of memory [Fig. 1B & 7]; and a controller [102] comprising a plurality of input/output (I/O) paths between multiple processors or processes with in the controller [claim does not indicate a timeline or context for plurality of paths for multiple processors or processes to exist or occur, nor matching between the plurality of I/O paths and the plurality of processors or processes; therefore the plurality of path may occur at different points over a span of time, as well as each path may be associated with at least one processor or processes; process path begins within the controller and extends to the memory dies [0071, lines 11-14; Fig. 7, a host and the NVM [bus lines including path from host to controller, and controller to devices (706, 708, 710, 712; see also 0078]; wherein the controller is configured to cause a first one of the I/O paths within the controller to communicate messages corresponding to read and write operations between the host and the NVM for the first set of memory independently from all of the other I/O paths [including 708], and to cause a second one of the I/O paths within the controller to communicate messages corresponding to read and write operations between the host and the NVM for the second set of memory independently from all of the other I/O paths [including 712] [0078 details sending of chip enable and messages over separate lines to separate memories; “messages” has not been defined and will be interpreted according to broadest reasonable interpretation; See also Figures 1A & 1B detailing I/O paths between host and NVM].
Regarding claim 2, Ravimohan et al. teaches wherein the NVM includes a plurality of NVM dies, and wherein the first set of memory comprises a first one or more NVM dies of the plurality of NVM dies and the second set of memory comprises a second separate one or more NVM dies of the plurality of NVM dies [0078; Fig. 7].
Regarding claim 3, Ravimohan et al. teaches wherein the NVM includes a plurality of NVM devices (dies, blocks, etc.), and wherein the first set of memory comprises a first one or more NVM devices of the plurality of NVM devices and the second set of memory comprises a second separate one or more NVM devices of the plurality of NVM devices [0078, fig. 7].
Regarding claim 4, Ravimohan et al. teaches wherein the NVM includes a plurality of NVM planes, and wherein the first set of memory comprises a first one or more NVM planes of the plurality of NVM planes and the second set of memory comprises a second separate one or more NVM planes of the plurality of NVM planes [0067; planes/die correspondence].
Regarding claim 5, Ravimohan et al. teaches wherein the controller is further configured to cause a third one of the I/O paths to communicate messages for both the first set of memory and the second set of memory [path from host to controller, and from controller to groups via 708 & 712, as paths may have multiple destinations; also claim does not indicate that messages for both sets are received simultaneously and thus the third path may change and/or incorporate the first and second paths serially].
Regarding claim 7, Ravimohan et al. teaches wherein the links comprise inter process communications (IPCs) [1402/12/14 and 110 via bus 117; Fig. 2A].
Regarding claim 8, Ravimohan et al. teaches wherein at least one of the IPCs comprises a software queue [0038, lines 1-11;buffers in RAM].
Regarding claim 9, Ravimohan et al. teaches wherein at least one of the IPCs comprises a physical IPC port [hardware port connects bus (117) to each item].
Regarding claim 10, Ravimohan et al. teaches wherein the controller includes a first power-on sequence for establishing the plurality of I/O paths [0038-0039; firmware and bootcode loaded at system start initialize memory system].
Regarding claim 11, Ravimohan et al. teaches wherein establishing the plurality of I/O paths comprises: determining a number of I/O paths to be established; and establishing the I/O paths based on the number [0038-0039; firmware and bootcode loaded at system start initialize memory system].
Regarding claim 12, Ravimohan et al. teaches wherein determining the number of I/O paths includes determining a number of sets of memory in the NVM [0038-0039; firmware and bootcode loaded at system start initialize memory system; number of paths dependent upon memory makeup as seen in Figure 7].
Claim 13 recites subject matter similar to that of claim 1, and is rejected for the same reasons as claim 1.
Claim 14 recites subject matter similar to that of claim 5, and is rejected for the same reasons as claim 5.
Claim 15 recites subject matter similar to that of claim 6, and is rejected for the same reasons as claim 6.
Claim 16 recites subject matter similar to that of claim 10, and is rejected for the same reasons as claim 10.
Claim 17 recites subject matter similar to that of claim 11, and is rejected for the same reasons as claim 11.
Claim 18 recites subject matter similar to that of claim 12, and is rejected for the same reasons as claim 12.
Regarding claim 19, Ravimohan et al. teaches wherein each message communicated by the I/O paths for the NVM comprises a region identifier that identifies one of a plurality of sets of memory of the NVM for which each of the messages is communicated [0063, lines 1-4].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ravimohan et al. (US# 2016/0202910) in view of Luo et al. (US# 2010/0122022).
Ravimohan et al. fails to teach wherein the controller includes a plurality of processors, and wherein I/O paths comprise links between all of the processors. Luo teaches a plurality of processors (FPU and CPU) within the NVM controller (Fig. 2, controller 200] where as seen in Figure 2 links (buses) are found between the processors themselves (claims indicate I/O paths are not part of I/O paths of claim 1).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the flash system of Ravimohan et al. to include the multi-processor system of Luo because then the distributed architecture enables the NVM to implement a blend of reliability and performance [0029, lines 20-24].
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed June 5, 2026 have been fully considered but they are not persuasive.
Regarding Applicant’s argument of page 7 of the response regarding “…Ravimohan does not explicitly teach that these buses comprise "a plurality of input/output (I/O) paths between multiple processors or processes within the controller" as is more clearly required by the claims”, the Examiner disagrees. Applicant’s claim language does not recite that the plurality of I/O paths between multiple processors or processes within the controller occur at the same time, nor does the claim language indicate the correspondence between the multiple processes or processors and the plurality of I/O paths. Therefore, a broad and reasonable interpretation of the claims would indicate that each path may occur at different times over a length of time, and each path may be associated with as few as a single processor or process. As noted above, Ravimohan et al. teaches at least one process for host access to the memory, where the I/O path includes processes within and without the controller. Multiple iterations of these operational processes taken over a period of time would read upon the claim language as recited.
The rejections are maintained as disclosed supra.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100.
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/BRIAN R PEUGH/Primary Examiner, Art Unit 2133
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