Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Comments
The Preliminary Amendment filed on April 1, 2025 is acknowledged. Claims 1-20 have been cancelled and new claims 21-43 have been examined for this Office Action.
Claim Objections
Claims 40 and 42 are objected to because of the following informalities: it appears the word “a” before “respective CRC codes” in each claim can be deleted. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 21-43 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. For sake of brevity, method claims 32-34 will be used in the below explanation. Claims 21-31 and 35-43 are rejected under similar reasoning. Specifically:Step 2A, Prong 1: Claim 32, for example, recites the limitations of “a method” and the method comprising “determining…an errors in a subset of a plurality of flits;” “counting…a number of flits…”, “counting…a number of errors…”, and “determining…. a bit error rate for the link”. All of this falls under the abstract idea of a mathematical concept. Specifically, the quoted claim limitations above are a math calculation. The limitations specify a mathematical formula of “error count” and “flit count” to calculate a “bit error rate”. MPEP 2106.04 section I.C. recites, “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation. There is no particular word or set of words that indicates a claim recites a mathematical calculation. That is, a claim does not have to recite the word "calculating" in order to be considered a mathematical calculation. For example, a step of "determining" a variable or number using mathematical methods or "performing" a mathematical operation may also be considered mathematical calculations when the broadest reasonable interpretation of the claim in light of the specification encompasses a mathematical calculation.”Step 2A, Prong 2: This judicial exception is not integrated into a practical application. The additional limitations to determine the error count and flit count using “error detection circuitry”, “counter(s)”, and “forward error correction circuit” is merely applying the judicial exception on a generic computer. Step 2B: The claims do not include additional elements, individually or combined, that are sufficient to amount to significantly more than the judicial exception. Again, the claim as a whole is directed to the abstract idea of mathematical calculations for calculating a bit error rate. The requirement of the error detection circuitry, counters, and forward error correction circuit processor are again applying the math on a generic computer. In the circumstance that the step of “receiving at a port…a plurality of flits on a link compliant with a PCIe-based protocol” is considered as extra-solution activity under prong 2, under step 2B, this is similar to previously court recognized well-understood, routine and conventional functions such as receiving or transmitting data; see 2106.05(d). Therefore, the claim is not patent eligible.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 33 and 39-43 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 33 recites the limitation "the one or more errors" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
Claim 39 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: claim 39 recites “..to access a register, wherein the register indicates the bit error rate”. The “bit error rate” refers back to claim 35 where “flit logging circuitry to determine a bit error rate…” The claims omit any structural relationship between the claimed “flit logging circuitry” and “register”. Presumably the “bit error rate” must have been stored in the register from the flit logging circuitry but that essential structural cooperative relationship is omitted.
Claim 40 recites the limitation "the one or more errors" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 41 recites the limitation "the instructions executable to cause a machine to" in line 2. There is insufficient antecedent basis for this limitation in the claim because the claim recites, “At least one non-transitory machine-readable storage medium with instructions” meaning in cases where there are two or more, it is not clear which “instructions” are being referred to when “the instructions” is recited.
Claim 41 recites the limitation "the one or more errors" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 26-28, 32, 33, 35, and 37-42 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0085619 A1 to Iyer et al (herein Iyer).
Referring to claim 21, Iyer discloses an apparatus comprising: a port to couple to an interconnect (see Figure 7, arrow pointing into Receiving device 710 and 715), wherein the port comprises: physical layer (PHY) circuitry to implement a physical layer of a link on the interconnect based on a Peripheral Component Interconnect Express (PCle)-based protocol (paragraph [0038], PCIe with physical layer depicted in Figure 2, element 220), wherein the PHY circuitry is further to: receive a plurality of flits on the link implemented on the interconnect (see Figure 7, arrow pointing into Receiving device 710 and 715); determine one or more errors in a subset of the plurality of flits (Figure 7, element 755); a flit error counter to count a number of errors in the subset of flits (Figure 7, element 765 and paragraphs [0077-0078]); and flit logging circuitry to determine a bit error rate (BER) for the link based on the flit counter and the flit error counter (Figure 7, element 765 and paragraphs [0077-0078]). Iyer does not explicitly disclose a “a flit counter to count a number of flits in the plurality of flits”. However, Iyer does disclose in paragraphs [0077-0078] a lane error monitor containing an algorithm to determine a rate of errors for each monitored lane. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to keep track of a number of Flits received utilizing a counter in order to a required variable in order to calculate the disclosed bit error rate since a bit error rate is a ratio of a number of Flits with errors over a number of total Flits received. Doing so would allow Iyer to calculate the rate of errors in order to compare the calculated error rate to defined threshold as taught in [0078].
Referring to claim 26, Iyer discloses wherein the PHY circuitry further comprises a forward error correction (FEC) circuitry to detect at least one of the one or more errors and correct the at least one of the one or more errors ([0072], ECC).
Referring to claim 27, Iyer discloses wherein the PHY circuitry further comprises cyclical redundancy check (CRC) circuitry to detect at least one of the one or more errors ([0072], CRC).
Referring to claim 28, Iyer discloses wherein the one or more errors comprise correctable errors ([0072], SEC).
Referring to method claims 32-33, system claims 35 and 40, and non-transitory machine-readable storage medium claims 41-42, the claims recite similar limitations as found in apparatus claims 21 and 26-28, therefore, are similarly rejected as unpatentable over Iyer.
Referring to claims 37 and 38, Iyer discloses wherein at least one of the first device or the second device comprises a graphics processing unit (GPU) (paragraph [0095]) and wherein at least one of the first device or the second device comprises a memory device (paragraph [0094]).
Referring to claim 39, Iyer discloses further comprising system software executable by a processor to access a register, wherein the register indicates the bit error rate (paragraph [0077], registers corresponding to the link).
Claims 25, 29-31, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0085619 A1 to Iyer et al (herein Iyer) in view of “PCI-SIG® 2020 Update” to Yanes et al (herein Yanes).
Referring to claims 25 and 36, Iyer substantially discloses the invention of claim 21 and 35, however, does not explicitly disclose wherein the PCIe-based protocol comprises a PCIe Revision 6 protocol. Iyer does disclose implementing a PCIe-based protocol. Yanes key features of the PCIe 6.0 Specification (slide 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Iyer with the teachings of Yanes found in the PCIe 6.0 Specification to arrive at the claims of this application in order to gain the benefits (e.g. higher bandwidth, increased data rates) provided by the PCIe 6.0 specification.
Referring to claims 29-31, Iyer substantially discloses the invention of claim 21, however, does not explicitly disclose wherein pulse amplitude modulation (PAM) signaling is used to deliver the plurality of flits on the link; wherein the PHY circuitry is further to insert a PAM-4 jitter measurement pattern on the link to measure jitter on the link; and wherein the PAM-4 jitter measurement pattern is to be direct current (DC)-balanced and utilize 2-bit encoding. Yanes discloses key features of the PCIe 6.0 version including the implementation of PAM4 signaling, allowing it to pack more bits into the same amount of time on a serial channel as already integrated in the PCIe 6.0 Specification (see slide 7). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Iyer with the teachings of Yanes found in the PCIe 6.0 Specification to arrive at the claims of this application in order to gain the benefits (e.g. higher bandwidth, increased data rates) provided by the PCIe 6.0 specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-43 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 12,155,474 B2 in view of “PCI-SIG® 2020 Update” to Yanes et al (herein Yanes). Although the claims at issue are not identical, they are not patentably distinct from each other because the cited claims of this application are encompassed within and, therefore, anticipated or obvious variations of the cited claims of the ‘474 patent. A table below maps the claims of this application to their corresponding claims in the ‘474 patent.
Claims Mapping
Claim #
This Application
Claim #
US 12,155,474 B2
21
An apparatus comprising:
1
An apparatus comprising
21
a port to couple to an interconnect, wherein the port comprises:
1
a port to receive a flow control unit (Flit)
21
physical layer (PHY) circuitry to implement a physical layer of a link on the interconnect based on a Peripheral Component Interconnect Express (PCle)-based protocol,
111
the link comprising a plurality of lanes;(*plurality of lanes - physical interconnect)a Peripheral Component Interconnect Express (PCIe)-compatible device;
21
the PHY circuitry is further to: receive a plurality of flits on the link implemented on the interconnect;
1
to receive a flow control unit (Flit) across a linkcount a number of Flits received,
21
determine one or more errors in a subset of the plurality of flits;
1
error detection circuitry to detect an error in the Flit, the error detection circuitry comprising forward error correction (FEC) circuitry,
21
a flit counter to count a number of flits in the plurality of flits;
1
a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving the Flit,
21
a flit error counter to count a number of errors in the subset of flits;
1
an error counter to count a number of errors detected, the error counter to increment based on the error detected in the Flit by the error detection circuitry
21
flit logging circuitry to determine a bit error rate (BER) for the link based on theflit counter and the flit error counter.
1
bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter;
22
wherein at least a portion of the errors in the subsetof flits are determined during a test mode of the link.
1
wherein bits of the margin control and status registers indicate whether a test mode is activated, and the receiver is to log the bit error rate based on the test mode being indicated as activated.
23
wherein the PHY circuitry is to perform receiver margining for the link, the test mode comprises the receiver margining, and the portion of the errors in the subset of flits are determined during the receiver margining.
110
wherein bits of the margin control and status registers indicate whether a test mode is activated, and the receiver is to log the bit error rate based on the test mode being indicated as activated.a margin command register, the margin command register comprising margin command information to start, stop, or clear the error counter
24
wherein the test mode comprises a loopback link state.
25
wherein the PCle-based protocol comprises a PCleRevision 6 protocol.
11
a Peripheral Component Interconnect Express (PCIe)-compatible device; receiving, at the PCIe-compatible device,
26
wherein the PHY circuitry further comprises a forwarderror correction (FEC) circuitry to detect at least one of the one or more errors and correct theat least one of the one or more errors.
1
the error detection circuitry comprising forward error correction (FEC) circuitry,
27
wherein the PHY circuitry further comprises cyclicalredundancy check (CRC) circuitry to detect at least one of the one or more errors.
4
the error detection circuitry further comprises cyclic redundancy check (CRC) circuitry, and the error counter to increment based on the FEC circuitry correcting the error in the Flit and the Flit passing a check performed by the CRC circuitry.
28
wherein the one or more errors comprise correctable errors.
5
wherein the FEC circuitry is to detect a correctable error in the Flit on a per-lane basis, and wherein the error counter is to count a number of correctable errors on a per-lane basis.
29
wherein pulse amplitude modulation (PAM) signaling is used to deliver the plurality of flits on the link.
30
wherein the PHY circuitry is further to insert a PAM-4 jitter measurement pattern on the link to measure jitter on the link.
31
wherein the PAM-4 jitter measurement pattern is tobe direct current (DC)-balanced and utilize 2-bit encoding.
Claims 32-43 of this application are similarly rejected as anticipated or obvious over claims 1-25 of the ‘474. For the claims of this application, that are missing a corresponding mapped limitation to the claim of the ‘474, Yanes discloses these limitations (e.g. PAM-4 jitter, PCIe 6.0, loopback) as already integrated in the PCIe 6.0 Specification. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the claims of the ‘474 with the teachings of Yanes found in the PCIe 6.0 Specification to arrive at the claims of this application in order to gain the benefits (e.g. higher bandwidth, increased data rates) provided by the PCIe 6.0 specification.
Conclusion
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112