Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-43 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 12,155,474 B2 in view of “PCI-SIG® 2020 Update” to Yanes et al (herein Yanes). Although the claims at issue are not identical, they are not patentably distinct from each other because the cited claims of this application are encompassed within and, therefore, anticipated or obvious variations of the cited claims of the ‘474 patent. A table below maps the claims of this application to their corresponding claims in the ‘474 patent.
Claims Mapping
Claim #
This Application
Claim #
US 12,155,474 B2
21
An apparatus comprising:
1
An apparatus comprising
21
a port to couple to an interconnect, wherein the port comprises:
1
a port to receive a flow control unit (Flit)
21
physical layer (PHY) circuitry to implement a physical layer of a link on the interconnect based on a Peripheral Component Interconnect Express (PCle)-based protocol,
111
the link comprising a plurality of lanes;(*plurality of lanes - physical interconnect)a Peripheral Component Interconnect Express (PCIe)-compatible device;
21
the PHY circuitry is further to: receive a plurality of flits on the link implemented on the interconnect;
1
to receive a flow control unit (Flit) across a linkcount a number of Flits received,
21
determine one or more errors in a subset of the plurality of flits;
1
error detection circuitry to detect an error in the Flit, the error detection circuitry comprising forward error correction (FEC) circuitry,
21
a flit counter to count a number of flits in the plurality of flits;
1
a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving the Flit,
21
a flit error counter to count a number of errors in the subset of flits;
1
an error counter to count a number of errors detected, the error counter to increment based on the error detected in the Flit by the error detection circuitry
21
flit logging circuitry at the port to determine a bit error rate (BER) for the link based on theflit counter and the flit error counter.
1
bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter;
22
wherein at least a portion of the errors in the subsetof flits are determined during a test mode of the link.
1
wherein bits of the margin control and status registers indicate whether a test mode is activated, and the receiver is to log the bit error rate based on the test mode being indicated as activated.
23
wherein the PHY circuitry is to perform receiver margining for the link, the test mode comprises the receiver margining, and the portion of the errors in the subset of flits are determined during the receiver margining.
110
wherein bits of the margin control and status registers indicate whether a test mode is activated, and the receiver is to log the bit error rate based on the test mode being indicated as activated.a margin command register, the margin command register comprising margin command information to start, stop, or clear the error counter
24
wherein the test mode comprises a loopback link state.
25
wherein the PCle-based protocol comprises a PCleRevision 6 protocol.
11
a Peripheral Component Interconnect Express (PCIe)-compatible device; receiving, at the PCIe-compatible device,
26
wherein the PHY circuitry further comprises a forwarderror correction (FEC) circuitry to detect at least one of the one or more errors and correct theat least one of the one or more errors.
1
the error detection circuitry comprising forward error correction (FEC) circuitry,
27
wherein the PHY circuitry further comprises cyclicalredundancy check (CRC) circuitry to detect at least one of the one or more errors.
4
the error detection circuitry further comprises cyclic redundancy check (CRC) circuitry, and the error counter to increment based on the FEC circuitry correcting the error in the Flit and the Flit passing a check performed by the CRC circuitry.
28
wherein the one or more errors comprise correctable errors.
5
wherein the FEC circuitry is to detect a correctable error in the Flit on a per-lane basis, and wherein the error counter is to count a number of correctable errors on a per-lane basis.
29
wherein pulse amplitude modulation (PAM) signaling is used to deliver the plurality of flits on the link.
30
wherein the PHY circuitry is further to insert a PAM-4 jitter measurement pattern on the link to measure jitter on the link.
31
wherein the PAM-4 jitter measurement pattern is tobe direct current (DC)-balanced and utilize 2-bit encoding.
Claims 32-43 of this application are similarly rejected as anticipated or obvious over claims 1-25 of the ‘474. For the claims of this application, that are missing a corresponding mapped limitation to the claim of the ‘474, Yanes discloses these limitations (e.g. PAM-4 jitter, PCIe 6.0, loopback) as already integrated in the PCIe 6.0 Specification. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the claims of the ‘474 with the teachings of Yanes found in the PCIe 6.0 Specification to arrive at the claims of this application in order to gain the benefits (e.g. higher bandwidth, increased data rates) provided by the PCIe 6.0 specification.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Justin Knapp whose telephone number is (571)270-3008. The examiner can normally be reached 8:00 am - 4:30 pm (ET).
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112
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