888DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4-6, 8, 11, 12, 14-16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nelson et al (US Pat. 7,620,875; hereinafter referred to as Nelson) in view of Greathouse et al (US Pat. 11,687,251; hereinafter referred to as Greathouse).
As per claims 1, 11, 22:
Nelson teaches a processing system, computer program product, and method comprising:
a memory comprising memory spaces (Fig. 12, 1300), a data memory space (Fig. 12, Data), and a first ECC memory space (Fig. 12, 1312); and
a memory controller for:
obtaining first data that are to be written into a memory of a processing system (Fig. 5, 610);
determining a first arrangement manner of a memory space occupied by a data symbol (Fig. 12, 1320 and 1310; col. 6, lines 17-29);
determining M data symbols of the first data (Fig. 6, 752) based on the first arrangement manner (Fig. 12, 1310), wherein each of the M data symbols comprises first data bits, and wherein M is an integer greater than or equal to 1 (col. 5, lines 7-10);
performing first error correction code (ECC) encoding on the M data symbols to obtain N redundant symbols (Fig. 12, 1312), wherein each of the N redundant symbols comprises a first redundant bit, and wherein N is an integer greater than or equal to 1 (col. 5, lines 10-11);
writing the M data symbols into a data memory space of the memory (Fig. 12, 1310 Data); and
writing the N redundant symbols into a first ECC memory space of the memory (Fig. 12, 1312 ECC).
Not explicitly disclosed is determining the first arrangement manner based on first error distribution area information of at least one memory space in memory spaces of the memory. However, Greathouse in an analogous art teaches receiving first error distribution area information (Fig. 7, 702) of at least one memory space in memory spaces of the memory (Fig. 6).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the error distribution area information of Greathouse to determine the arrangement order of Nelson. This modification would have been obvious for one of ordinary skill in the art at the time of filing because Nelson teaches partitioning memory dynamically (Fig. 12), and Greathouse would have provided a necessary mechanism to facilitate doing so.
As per claims 2, 12:
Nelson teaches method of claim 1 and processing system of claim 11, wherein the first error distribution area information indicates a specific area in the at least one memory space in which an error data bit falls when a data error occurs in the at least one memory space (Fig. 12, blocks in area 1310 labeled “Data”).
As per claims 4, 14: Nelson teaches the method of claim 1 and processing system of claim 11, further comprising obtaining the first error distribution area information (col. 6, lines 20-22; memory map is inherently obtained in order to determine mapped area as shown in Fig. 12).
As per claims 5, 15: Nelson teaches the method of claim 1 and processing system of claim 11 above. Not explicitly disclosed is further comprising: reading, from the memory, second data representing all data in the memory and comprising second data bits and a redundant bit; determining, based on second error distribution area information of the at least one memory space, a second arrangement manner of the memory space; determining P data symbols of the second data bits based on the second arrangement manner, wherein each of the P data symbols comprises third data bits, and wherein P is an integer greater than or equal to 1; performing second ECC encoding on the P data symbols to obtain Q redundant symbols, wherein each of the Q redundant symbols comprises a second redundant bit, and wherein Q is an integer greater than or equal to 1; writing the P data symbols into the data memory space; and writing the Q redundant symbols into the first ECC memory space.
However, Greathouse in an analogous art teaches: reading, from the memory, second data representing all data in the memory (Fig. 5, 704) and comprising second data bits and a redundant bit (Fig. 6, 602 and 604); determining, based on second error distribution area information of the at least one memory space, a second arrangement manner of the memory space (Fig. 7, 702); determining P data symbols of the second data bits based on the second arrangement manner, wherein each of the P data symbols comprises third data bits, and wherein P is an integer greater than or equal to 1 (Fig. 5, 708); performing second ECC encoding on the P data symbols to obtain Q redundant symbols, wherein each of the Q redundant symbols comprises a second redundant bit, and wherein Q is an integer greater than or equal to 1 (Fig. 7, 708); writing the P data symbols into the data memory space; and writing the Q redundant symbols into the first ECC memory space (Fig. 7, 710).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to perform the teachings of Greathouse on the memory of Nelson. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have allowed for dynamic repartitioning without risking interrupting or causing errors to the system (col. 4, lines 1-13).
As per claims 6, 16: Greathouse further teaches the method of claim 5 and processing system of claim 15, further comprising obtaining the second error distribution area information (Fig. 7, 702).
As per claims 8, 18: Greathouse further teaches the method of claim 1 and processing system of claim 11, wherein the data symbol and the N redundant symbols are Reed-Solomon (RS) code symbols or Bose-Chaudhuri-Hocquenghem (BCH) code symbols (col. 4, lines 53-56).
Claim(s) 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nelson in view of Greathouse in view of Golding (US Pat. 11,061,930).
As per claims 7, 17:
Nelson et al teach the method of claim 6 and processing system of claim 16 above. Not explicitly disclosed is wherein obtaining the second error distribution area information comprises determining the second error distribution area information based on a historical data error. However, Golding in an analogous art teaches determining a distribution area information based on a historical data (col. 14, lines 42-56).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to determine the second error distribution area information of Greathouse based on a historical data error. This modification would have been obvious for one of ordinary skill in the art at the time of filing because historical data could have been used as a metric for determining distribution areas, as shown by Golding.
Claim(s) 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nelson in view of Greathouse in view of Kaynak et al (US Pat. Pub. 2018/0267851; hereinafter referred to as Kaynak).
As per claims 9, 20: Nelson et al teach the method of claim 1 and processing system of claim 11 above. Not explicitly disclosed is further comprising: performing second ECC encoding on the M data symbols and the N redundant symbols to obtain R redundant symbols, wherein each of the R redundant symbols comprises a second redundant bit, and wherein R is an integer greater than or equal to 1; writing the M data symbols into the data memory space; and writing the R redundant symbols into a second ECC memory space of the memory. However, Kaynak in an analogous art teaches performing second ECC encoding (Fig. 1, 132) on the M data symbols and the N redundant symbols (Fig. 1, 134) to obtain R redundant symbols (paragraph 19), and writing the symbols into an ECC memory space (Fig. 3).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to perform the inner and outer encoding of Kaynak in the system of Nelson et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because it would have provided more robust error correction (paragraph 11).
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Nelson in view of Greathouse in view of Das et al (US Pat. Pub. 2016/0283318; hereinafter referred to as Das).
As per claim 21: Nelson et al teach the processing system of claim 11. Not explicitly disclosed is wherein the memory is an on-die error correction code (ECC) memory. However, Das in an analogous art teaches a memory having on-die ECC (Fig. 1; paragraph 21).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to include on-die ECC in the system of Nelson et al. This modification would have been obvious for one of ordinary skill in the art at the time of filing because the use of ECC within a memory could have been labeled on-die ECC, as taught by Das in paragraph 21.
Allowable Subject Matter
Claims 3 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art of record teach or fairly suggest: wherein the data symbol occupies an 8-bit memory space and the first arrangement manner comprises arrangement in 4 rows and 2 columns, 2 rows and 4 columns, 8 rows and 1 column, or 1 row and 8 columns, wherein the data symbol occupies a 16-bit memory space and the first arrangement manner comprises arrangement in 4 rows and 4 columns, 8 rows and 2 columns, 2 rows and 8 columns, or 16 rows and 1 column, or wherein the data symbol occupies a 32-bit memory space and the first arrangement manner comprises arrangement in 1 row and 32 columns, 32 rows and 1 column, 2 rows and 16 columns, 16 rows and 2 columns, 4 rows and 8 columns, or 8 rows and 4 columns; as recited in claim 3 and similarly in claim 13, particularly in combination with each and every other limitation of the parent claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art is generally directed to adaptive memory ECC methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111