DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6, 8, 17, and 18 is/are rejected under 35 U.S.C. 102(a) as being anticipated by Lo (US 2013/0222060 A1).
Regarding claim 1, Lo teaches an electronic circuit (fig. 3, Single-Ended Mutually Coupled Matching Network 306) comprising:
an impedance matching circuit (Matching network 306; [0033]–[0037]) comprising:
a first inductance, coupled between a first node and a second node (L1' (336) coupled between source (first node) and load/shared node (second node) ([0037])); and
a second inductance, coupled between the second node and a third node, wherein the third node is coupled to ground (L2' (338) coupled between the shared node (second node) and ground (third node) ([0037]));
wherein the first and second inductances are configured to have a positive magnetic coupling between each other (Dot convention in FIG. 3 shows both dots oriented so currents enter dotted terminals → same-direction flux → positive coupling. Equations (3)–(4) confirm additive mutual inductance term ([0037]–[0038])).
Regarding claim 3, Lo teaches the electronic circuit according to claim 1, wherein the first and the second inductances are formed by planar conductive windings (Lo describes forming the mutually coupled inductors using planar technology including silicon, SOI, POG, IPD, LTCC, and PCB ([0024]). FIG. 4 shows planar spiral winding layouts for both the discrete and coupled versions. Under BRI, planar spiral windings formed on a substrate read on "planar conductive windings.)
Regarding claim 6, Lo teaches the electronic circuit according to claim 1, wherein the first node is configured to be coupled to an amplifier (Lo FIG. 2 shows matching network 206b coupled between power amplifier (PA) 218 and duplexer 220 in the transmit chain, and matching network 206a between duplexer 220 and LNA 214 in the receive chain ([0031]–[0032]). In the transmit configuration, the PA output is the source coupled to the first node).
Regarding claim 8, Lo teaches the electronic circuit according to claim 1, wherein the first and the second inductances are configured for a current to flow there through in a same direction (In Lo FIG. 3, currents i1' (328b) and i2' (330b) both flow from the source side toward ground through the series path. The dot convention confirms both currents enter the dotted terminals, meaning current flows in the same direction through the coupled structure, producing positive coupling).
Regarding claim 17, Lo teaches the electronic circuit according to claim 1, wherein a first electromagnetic field generated by the first inductance and a second electromagnetic field generated by the second inductance are superimposed in a same direction (Lo's positive coupling (dot convention, Equations (3)–(4)) means the electromagnetic fields of L1' and L2' are superimposed in the same direction).
Regarding claim 18, Lo teaches an electronic device comprising:
an electronic circuit having an impedance matching circuit (Wireless device 202 / electronic device 102 ([0021], [0026])) comprising:
a first inductance, coupled between a first node and a second node (L1' (336) coupled between source (first node) and load/shared node (second node) ([0037])); and
a second inductance, coupled between the second node and a third node, wherein the third node is coupled to ground (L2' (338) coupled between the shared node (second node) and ground (third node) ([0037]));
wherein the first and second inductances are configured to have a positive magnetic coupling between each other (Dot convention in FIG. 3 shows both dots oriented so currents enter dotted terminals → same-direction flux → positive coupling. Equations (3)–(4) confirm additive mutual inductance term ([0037]–[0038])); and
an amplifier coupled to the first node (PA 218 (source) coupled to the first node in the transmit chain ([0032], [0048]); LNA 214 as load in receive chain ([0031], [0047])).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo as applied to claim 1 above, and further in view of KONG (US 2018/0167048 A1).
Regarding claim 2, Lo teaches the electronic circuit according to claim 1.
Lo is silent to teaching that wherein the third node is coupled to the ground via a capacitive element.
In the same field of endeavor, KONG teaches a device wherein the third node is coupled to the ground via a capacitive element (KONG teaches an impedance matching circuit (700, FIGS. 13–14) in which a capacitor Cm (730) is connected between a common node CN (analogous to the third node) and ground ([0109]). KONG teaches that the capacitor enables adjustment of the effective mutual inductance of the transformer ([0112])).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lo's matching network by coupling the third node to ground via a capacitive element, as taught by KONG, in order to enable fine tuning of the effective mutual inductance and improve the pass gain of the matching circuit, as KONG demonstrates (FIG. 27, [0162]).
Regarding claim 15, the combination of Lo and KONG teaches the electronic circuit according to claim 2, wherein a value of the capacitive element is configured to limit an occurrence of a current loop (KONG teaches that the capacitor Cm at the common node has an impedance of −j/ωCm ([0112]), and its value is selected to achieve a desired effect on the mutual inductance. A capacitor in the ground return path of an inductor structure inherently blocks DC current flow and limits the occurrence of DC current loops through the winding structure. The value of the capacitor controls the frequency-dependent impedance of the ground path and thus configures how current circulates through the inductor network. One of ordinary skill would have recognized that selecting the capacitor value to limit the occurrence of a current loop is an inherent functional consequence of KONG's capacitor placement and a routine design consideration in RF matching circuits).
Claim(s) 4, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo as applied to claim 1 above, and further in view of Whelan (US 2009/0066411 A1).
Regarding claim 4, Lo teaches the electronic circuit according to claim 1.
Lo is silent to teaching that wherein the second node is configured to be biased by a test device.
In the same field of endeavor, Whelan teaches a device wherein the second node is configured to be biased by a test device (Whelan teaches an RF amplifier circuit in which the performance of the amplifier and its associated impedance matching network is characterized using a load pull bench test set-up (FIG. 6, [0046]). In Whelan's test set-up, a Gate Bias Tee 24 and a Drain Bias Tee 32 are connected on either side of the device under test (DUT) to provide DC bias to the circuit nodes while simultaneously passing RF signals ([0046]). Whelan teaches that such bias tees are standard test devices used in RF circuit characterization to inject DC bias at circuit nodes — specifically at the input and output of the device under test — while the device is driven through its matching network with various source and load impedances presented by tuners 26 and 16 ([0046]–[0048]). Whelan further teaches that the purpose of this test configuration is to determine optimal impedance matching conditions for the device by performing source pulls and load pulls at various drive levels ([0048]–[0049])).
Therefore, it would have been obvious to one of ordinary skill in the art to configure the second node of Lo's matching circuit to be biased by a test device, as taught by Whelan's bias tee test configuration, in order to enable performance characterization of the matching network under controlled bias and impedance conditions during the design and validation process.
Regarding claim 19, the combination of Lo and Whelan teaches the electronic device according to claim 18, further comprising a test device configured to bias the second node (Whelan teaches an RF amplifier circuit in which the performance of the amplifier and its associated impedance matching network is characterized using a load pull bench test set-up (FIG. 6, [0046]). In Whelan's test set-up, a Gate Bias Tee 24 and a Drain Bias Tee 32 are connected on either side of the device under test (DUT) to provide DC bias to the circuit nodes while simultaneously passing RF signals ([0046]). Whelan teaches that such bias tees are standard test devices used in RF circuit characterization to inject DC bias at circuit nodes — specifically at the input and output of the device under test — while the device is driven through its matching network with various source and load impedances presented by tuners 26 and 16 ([0046]–[0048]). Whelan further teaches that the purpose of this test configuration is to determine optimal impedance matching conditions for the device by performing source pulls and load pulls at various drive levels ([0048]–[0049])).
Regarding claim 20, the combination of Lo and Whelan teaches the electronic device according to claim 19, wherein the test device is configured to bias the second node with a bias tee (Whelan teaches an RF amplifier circuit in which the performance of the amplifier and its associated impedance matching network is characterized using a load pull bench test set-up (FIG. 6, [0046]). In Whelan's test set-up, a Gate Bias Tee 24 and a Drain Bias Tee 32 are connected on either side of the device under test (DUT) to provide DC bias to the circuit nodes while simultaneously passing RF signals ([0046]). Whelan teaches that such bias tees are standard test devices used in RF circuit characterization to inject DC bias at circuit nodes — specifically at the input and output of the device under test — while the device is driven through its matching network with various source and load impedances presented by tuners 26 and 16 ([0046]–[0048]). Whelan further teaches that the purpose of this test configuration is to determine optimal impedance matching conditions for the device by performing source pulls and load pulls at various drive levels ([0048]–[0049])).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo as applied to claim 1 above, and further in view of HONDA (US 2024/0291445 A1).
Regarding claim 5, Lo teaches the electronic circuit according to claim 1.
Lo is silent to teaching that wherein the third node is configured to be biased by a power supply of the electronic circuit.
In the same field of endeavor, HONDA teaches a device wherein the third node is configured to be biased by a power supply of the electronic circuit (HONDA teaches that the matching circuit 160 is connected between the output terminal T11 of the amplifier 140 and a power source 180 ([0035], [0039], [0046]). Specifically, one end of the capacitor 161 is connected to the other end of the line 163 and the power source 180, and the other end of capacitor 161 is connected to a reference potential ([0039])).
Therefore, it would have been obvious to one of ordinary skill in the art to configure the third node of Lo's impedance matching circuit to be biased by a power supply of the electronic circuit, as taught by HONDA's connection of the matching circuit to power source 180, in order to use the matching network's inductance path as a DC supply feed to the amplifier, thereby simplifying the overall circuit design by combining the impedance matching and DC biasing functions into a single network.
Claim(s) 7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo as applied to claim 1 above, and further in view of HUSAIN (US 2023/0126116 A1).
Regarding claim 7, Lo teaches the electronic circuit according to claim 1.
Lo is silent to teaching that wherein the magnetic coupling is greater than 0.5.
In the same field of endeavor, HUSAIN teaches a device wherein the magnetic coupling is greater than 0.5 (HUSAIN teaches at [0081]–[0086] that the inductors L1, L2, and Lf may be implemented with a single inductor structure 1010 (FIG. 10A) formed on a die, where the different contact areas along the inductor structure define the individual inductors, and "the inductor structure 1010 forms an auto transformer in which the magnetic coupling between the different portions of the inductor structure 1010 provide the magnetic coupling (i.e., K12, K23, and K13) between the inductors L1, L2, and Lf" ([0086]). An auto-transformer, by definition, achieves its coupling through shared winding sections — the coupling coefficient of an auto-transformer is inherently close to unity (i.e., approaching 1.0), and is well understood by those of ordinary skill to be substantially greater than 0.5).
Therefore, it would have been obvious to one of ordinary skill in the art to implement Lo's mutually coupled matching network with a magnetic coupling greater than 0.5, as taught by HUSAIN's auto-transformer and on-chip stacked inductor implementations, in order to maximize the inductance reduction benefit of the mutual coupling and minimize the die area of the matching network.
Regarding claim 10, the combination of Lo and HUSAIN teaches the electronic circuit according to claim 3, wherein the second inductance has a second number of windings greater than a first number of windings of the first inductance (reasons above and HUSAIN, [0068]).
Claim(s) 9, 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo as applied to claim 1 above, and further in view of LI (US 2019/0296101 A1).
Regarding claim 9, Lo teaches the electronic circuit according to claim 1.
Lo is silent to teaching that wherein the first inductance and the second inductance are stacked.
In the same field of endeavor, LI teaches a device wherein the first inductance and the second inductance are stacked (LI teaches an integrated circuit transformer (150, FIG. 1A) in which two inductors L₁ (101) and L₂ (102) are deployed in a 3D stacked configuration across two tiers (tier A and tier B), connected by vias ([0027]–[0028])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to implement Lo's mutually coupled inductors in a stacked configuration as taught by LI, in order to maximize winding overlap, increase coupling coefficient, and reduce die area — all of which further Lo's stated objective of reducing area consumption while maintaining matching performance ([0025]).
Regarding claim 11, the combination of Lo and LI teaches the electronic circuit according to claim 3, wherein one or more first conductive tracks, insulated from the second inductance, totally or partly surround an outer region of the winding of the second inductance. FIG. 3A: outside coupling turns 301A/301B surround outer region, insulated ([0040])).
Regarding claim 12, the combination of Lo and LI teaches the electronic circuit according to claim 3, wherein one or more second conductive tracks, insulated from the second inductance, are disposed between a central portion of the second inductance that is not covered by the winding of the second inductance, and an inner region of the winding of the second inductance (LI, FIG. 3B: inside coupling turns 311A/311B inside winding area, insulated ([0041])).
Regarding claim 13, the combination of Lo and LI teaches the electronic circuit according to claim 3, wherein one or more third conductive tracks, insulated from the first inductance, totally or partly surround an outer region of the winding of the first inductance (LI, FIG. 3A: outside coupling turns surround both inductors' outer region ([0040])).
Regarding claim 14, the combination of Lo and LI teaches the electronic circuit according to claim 3, wherein one or more fourth conductive tracks, insulated from the first inductance, are disposed between a central portion of the first inductance that is not covered by the winding of the first inductance, and an inner region of the winding of the first inductance (LI, FIG. 3B: inside coupling turns in interior of innermost inductor winding ([0041])).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo as applied to claim 1 above, and further in view of CHEN (US 2019/0356283 A1).
Regarding claim 16, Lo teaches the electronic circuit according to claim 1.
Lo is silent to teaching that wherein the impedance matching circuit comprises another capacitive element coupling the first and the second nodes.
In the same field of endeavor, CHEN teaches a device wherein the impedance matching circuit comprises another capacitive element coupling the first and the second nodes (CHEN's impedance matching circuit 130 includes an inductor L1 coupled between node N1 and node N2 ([0015]). Critically, CHEN further teaches that the impedance matching circuit 130 includes a capacitor C2 and an inductor L2 coupled in series, and that this series combination of C2 and L2 is coupled between node N1 and node N2 — i.e., coupled in parallel with the inductor L1 ([0015]). CHEN states: "the capacitor C2 and the inductor L2 are coupled in series and are coupled in parallel with the inductor L1" ([0015])).
Therefore, it would have been obvious to one of ordinary skill in the art to modify Lo's impedance matching circuit to include another capacitive element coupling the first and second nodes, as taught by CHEN's capacitor C2 coupled between nodes N1 and N2 of the impedance matching circuit, in order to provide frequency-selective impedance behavior that improves harmonic rejection and enhances the linearity and bandwidth performance of the matching network.
Claim(s) 21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo in view of Whelan and Ni (US 2009/0153431 A1).
Regarding claim 21, the combination of Lo and Whelan teaches the electronic device according to claim 20.
The combination of Lo and Whelan is silent to teaching that wherein an antenna coupled to the bias tee.
In the same field of endeavor, Ni teaches a device comprising an antenna coupled to the bias tee (Ni teaches an impedance matching network (200, FIG. 2A) in which an antenna 206 is directly coupled to the output side of the matching network, and a DC bias source 208 provides bias to an intermediate node of the matching network through a bias path ([0024]–[0027]). In Ni's configuration, the antenna is the load that the matching network is designed to match, and the bias injection node and the antenna are on the same matching network — the antenna is coupled to the circuit that includes the bias injection path).
Therefore, it would have been obvious to one of ordinary skill in the art to modify Lo's electronic device to include a test device comprising a bias tee configured to bias the second node, with an antenna coupled to the bias tee, as taught by Whelan's bias tee test configuration and Ni's antenna-coupled matching network, in order to provide a complete RF front-end test and operation configuration in which the matching network is characterized under controlled DC bias conditions while coupling the amplifier to the antenna through the bias tee's RF path.
Regarding claim 23, Lo teaches a 5th Generation (5G) radio frequency communication system comprising:
an electronic circuit having an impedance matching circuit (Wireless device 202 / electronic device 102 ([0021], [0026])) comprising:
a first inductance, coupled between a first node and a second node (L1' (336) coupled between source (first node) and load/shared node (second node) ([0037])); and
a second inductance, coupled between the second node and a third node, wherein the third node is coupled to ground (L2' (338) coupled between the shared node (second node) and ground (third node) ([0037]));
wherein the first and second inductances are configured to have a positive magnetic coupling between each other (Dot convention in FIG. 3 shows both dots oriented so currents enter dotted terminals → same-direction flux → positive coupling. Equations (3)–(4) confirm additive mutual inductance term ([0037]–[0038]));
an amplifier coupled to the first node (PA 218 (source) coupled to the first node in the transmit chain ([0032], [0048]); LNA 214 as load in receive chain ([0031], [0047])); and
an antenna (fig. 3, antenna 210).
Lo is silent to teaching that comprising a test device configured to bias the second node with a bias tee; and wherein an antenna coupled to the bias tee.
In the same field of endeavor, Whelan teaches a device wherein the second node is configured to be biased by a test device (Whelan teaches an RF amplifier circuit in which the performance of the amplifier and its associated impedance matching network is characterized using a load pull bench test set-up (FIG. 6, [0046]). In Whelan's test set-up, a Gate Bias Tee 24 and a Drain Bias Tee 32 are connected on either side of the device under test (DUT) to provide DC bias to the circuit nodes while simultaneously passing RF signals ([0046]). Whelan teaches that such bias tees are standard test devices used in RF circuit characterization to inject DC bias at circuit nodes — specifically at the input and output of the device under test — while the device is driven through its matching network with various source and load impedances presented by tuners 26 and 16 ([0046]–[0048]). Whelan further teaches that the purpose of this test configuration is to determine optimal impedance matching conditions for the device by performing source pulls and load pulls at various drive levels ([0048]–[0049])).
Therefore, it would have been obvious to one of ordinary skill in the art to configure the second node of Lo's matching circuit to be biased by a test device, as taught by Whelan's bias tee test configuration, in order to enable performance characterization of the matching network under controlled bias and impedance conditions during the design and validation process.
The combination of Lo and Whelan is silent to teaching that wherein an antenna coupled to the bias tee.
In the same field of endeavor, Ni teaches a device comprising an antenna coupled to the bias tee (Ni teaches an impedance matching network (200, FIG. 2A) in which an antenna 206 is directly coupled to the output side of the matching network, and a DC bias source 208 provides bias to an intermediate node of the matching network through a bias path ([0024]–[0027]). In Ni's configuration, the antenna is the load that the matching network is designed to match, and the bias injection node and the antenna are on the same matching network — the antenna is coupled to the circuit that includes the bias injection path).
Therefore, it would have been obvious to one of ordinary skill in the art to modify Lo's electronic device to include a test device comprising a bias tee configured to bias the second node, with an antenna coupled to the bias tee, as taught by Whelan's bias tee test configuration and Ni's antenna-coupled matching network, in order to provide a complete RF front-end test and operation configuration in which the matching network is characterized under controlled DC bias conditions while coupling the amplifier to the antenna through the bias tee's RF path.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo as applied to claim 1 above, and further in view of LYALIN (US 2018/0006626 A1).
Regarding claim 22, Lo teaches the electronic device according to claim 18.
Lo is silent to teaching that wherein the amplifier comprises a bipolar-type transistor, and wherein the first node is coupled to a collector of the transistor.
In the same field of endeavor, LYALIN teaches a device wherein the amplifier comprises a bipolar-type transistor, and wherein the first node is coupled to a collector of the transistor (LYALIN teaches an amplifying bipolar transistor (122) where RF input is applied to the base, and the amplified signal is output through the collector to a tap node (146) of a matching autotransformer).
Therefore, it would have been obvious to a Person Having Ordinary Skill in the Art (POSITA) to combine the autotransformer impedance matching circuit of LYALIN with the mutually coupled planar inductor design principles taught by Lo because both references belong to the same field of radio frequency (RF) circuit design, specifically impedance matching networks for RF power amplifiers implemented on integrated circuits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEN WU HUANG whose telephone number is (571)272-7852. The examiner can normally be reached Mon-Fri 10-6.
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/WEN W HUANG/Primary Examiner, Art Unit 2648
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