DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 18/920,580 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statement 11/13/2024 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed, approved immediately upon submission, and reduces waiting time for Terminal Disclaimer to be manually approved. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting over the claims of 1-17 of U.S. Pat. No. 12,141,443, claims of 1-23 of U.S. Pat. No. 11,360,670 and claims of 1-20 of U.S. Pat. No. 10,852,953, since the claims, if allowed, would improperly extend the “right to exclude” already granted in patents. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patents and application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. (US pub. # 2012/0134213), hereinafter, “Choi”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1 and 9, Choi discloses a method by a memory system (flash memory device of fig. 4, as discloses in paragraph 0059), comprising: reading, from a register (register to store lookup table 501, as discloses in paragraph 0062) of the memory system, a voltage level associated with performing a memory operation on one or more memory cells of the memory system, wherein the voltage level stored in the register is based at least in part on a base voltage value and a temperature compensation trim (see paragraph 0063 and 0085), wherein the temperature compensation trim is based on in-service data including calibration data that is collected during one or more second memory operations on the one or more memory cells [see paragraphs 0081 and 0085, particularly 0085, which discloses “in certain embodiments of the inventive concept, increasing/decreasing slopes of offset values may be modified by the control logic 600 when voltage trim information is loaded to the register storing the lookup tables 501 from a memory cell array 100. Alternatively, multiple voltage trim information sets reflecting various increasing/decreasing slopes of offset values may be stored in the memory cell array 100, wherein any one of the multiple voltage trim information sets may be selected by the control logic 600 upon memory device power-up and then loaded to the lookup table register 501. Selection of a voltage trim information set or change in voltage trim information may be made under the instruction of an external device (e.g., a memory controller or host)”]; and performing the memory operation on the one or more memory cells in accordance with the voltage level that is read from the register of the memory system (see paragraphs 0054, 0081 and 0082).
3. As per claims 2 and 10, Choi discloses “The method of claim 1” [See rejection to claim 1 above], further comprising: performing, prior to performing the memory operation, the one or more second memory operations on the one or more memory cells, wherein the calibration data is collected by the memory system based at least in part on performing the one or more second memory operations (see paragraphs 0081 and 0083).
4. As per claims 3 and 11, Choi discloses, further comprising: updating, prior to performing the memory operation on the one or more memory cells, the voltage level stored in the register using the temperature compensation trim that is based on the in-service data, wherein reading the voltage level is based at least in part on updating the voltage level using the temperature compensation trim (see claim 12 of Choi, which discloses “the method comprising: storing trim information in a trim information region of the memory cell array, wherein the trim information comprises voltage trim information; upon powering-up the non-volatile memory device and using the trim voltage information, configuring at least one lookup table storing a plurality of compensating offset values; detecting a current temperature for the non-volatile memory device; after receiving an access command initiating execution of an access operation by the non-volatile memory device, generating a compensated operating voltage by selecting an offset value from the plurality of compensating offset values stored in the at least one lookup table in response to the current temperature; and performing the access operation using the compensated operating voltage”).
5. As per claims 4 and 12, Choi discloses, further comprising: performing a quantity of program erase cycles, wherein updating the voltage level stored in the register is based at least in part on performing the quantity of program erase cycles (see paragraph 0083).
6. As per claims 5 and 13, Choi discloses, further comprising: monitoring a temperature of a memory component associated with the one or more memory cells, wherein updating the voltage level stored in the register is based at least in part on the temperature of the memory component satisfying a threshold temperature (see paragraph 0083).
7. As per claims 6 and 14, Choi discloses, further comprising: receiving a request to perform the memory operation, wherein updating the voltage level stored in the register is based at least in part on receiving the request to perform the memory operation (see paragraph 0060).
8. As per claims 7 and 15, Choi discloses wherein the voltage level stored in the register is a sum of the base voltage value and one or more voltage trims including the temperature compensation trim (see claim 12 of Choi).
9. As per claims 8 and 16, Choi discloses wherein the register stores a plurality of voltage levels including the voltage level, wherein each voltage level of the plurality of voltage levels corresponds to a respective memory component, a respective program level, a respective word line group, or a combination thereof (see claim 12 of Choi).
10. As per claim 17, Choi discloses a method by a memory system, comprising: determining a plurality of temperature compensation trims based on in-service data associated with a memory operation of a memory component of the memory system (see paragraph 0063 and 0085), wherein the in-service data includes calibration data that checks a voltage level associated with the memory operation [see paragraphs 0081 and 0085, particularly 0085, which discloses “in certain embodiments of the inventive concept, increasing/decreasing slopes of offset values may be modified by the control logic 600 when voltage trim information is loaded to the register storing the lookup tables 501 from a memory cell array 100. Alternatively, multiple voltage trim information sets reflecting various increasing/decreasing slopes of offset values may be stored in the memory cell array 100, wherein any one of the multiple voltage trim information sets may be selected by the control logic 600 upon memory device power-up and then loaded to the lookup table register 501. Selection of a voltage trim information set or change in voltage trim information may be made under the instruction of an external device (e.g., a memory controller or host)”], wherein each temperature compensation trim corresponds to a respective temperature subrange of a plurality of temperature subranges (see paragraphs 0082 and 0083 or claim 3 of Choi, which discloses “wherein the at least one memory cell condition comprises a plurality of temperature ranges extending over a permissible temperature operating range for the non-volatile memory device, and compensating the operating voltage comprises: respectively assigning a different one of a plurality of compensating shifts to each one of the plurality of temperature ranges; determining a current temperature range among the plurality of temperature ranges that includes the current temperature; and applying one of the plurality of compensating shifts to the operating voltage that corresponds to the current temperature range”), and wherein at least one temperature subrange overlaps with an adjacent temperature subrange (see fig. 7); and selecting a temperature compensation trim from the plurality of temperature compensation trims for use as part of the memory operation (see paragraphs 0058 and 0082).
11. As per claim 18, Choi discloses wherein each temperature subrange of the plurality of temperature subranges covers at least a portion of an operating temperature range of the memory component (see fig. 7).
12. As per claim 19, Choi discloses wherein an upper value and a lower value of each temperature subrange of the plurality of temperature subranges is based on the in-service data (see paragraphs 0082 and 0083).
13. As per claim 20, Choi discloses wherein a number of the plurality of temperature subranges is based on the in-service data (see paragraphs 0082 and 0083)
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights