DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 18 October 2024 and 17 December 2025 iare in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. Accordingly, the IDS are being considered by this Examiner.
Double patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-6 and 9-20 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 7-11 and 14-15 of U.S. Patent 12153515. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims of the instant application are anticipated by the said claims of U.S. Patent 12153515. The side-by-side comparison below of claim 1 of the instant application and claim 1 of U.S. Patent 12153515 shows limitation by limitation matching between the conflicting claims.
Instant Application
U.S. Patent 12153515
1. A method comprising:
generating mapping information in which, for each frame of a plurality of frames stored in a storage component, at least one logical address is assigned to the frame; and
providing a batch read request to the storage component, to read all of the at least one logical address assigned to the frame by referring the mapping information.
1. A storage device comprising:
a memory device that stores data;
a storage controller that stores a data stream including a plurality of frames in the memory device based on a
write request from a host; and
a scaler that generates a mapping table in which, for each frame of the plurality of frames, at least one logical address assigned to the frame is mapped to a frame number assigned to the frame,
wherein, for each frame of the plurality of frames included in the data stream, the scaler performs an operation of obtaining the at least one logical address assigned to the frame by referring to the mapping table and providing a batch read request to the storage controller to read all the at least one logical address assigned to the frame,
wherein the storage controller controls the memory device to perform a read operation on a memory area corresponding to the at least one logical address based on the batch read request.
Per independent claim 13, similar claim mapping to claim 1 of U.S. Patent 12153515 would be clear to a person having ordinary skill in the art but have been omitted for the sake of brevity.
Per independent claim 19, similar claim mapping to claims 1 and 2 of U.S. Patent 12153515 would be clear to a person having ordinary skill in the art but have been omitted for the sake of brevity.
Per dependent claim 2, the claim is anticipated by claim 2 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 3, the claim is anticipated by claim 3 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 4, the claim is anticipated by claim 4 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 5, the claim is anticipated by claim 8 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 6, the claim is anticipated by claim 9 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 9, the claim is anticipated by claim 10 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 10, the claim is anticipated by claim 7 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 11, the claim is anticipated by claim 11 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 12, the claim is anticipated by claim 15 of U.S. Patent 12153515 (instant application’s claim 1 is similarly anticipated by claim 14 of U.S. Patent 12153515). Note that claim 14 of U.S. Patent 12153515 teaches each frame group includes at least one frame, as such the frame groups of U.S. Patent 12153515 may be mapped to the frames in instant claim 1.
Per dependent claim 14, the claim is anticipated by claim 2 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 15, the claim is anticipated by claim 2 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 16, the claim is anticipated by claim 1 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 17, the claim is anticipated by claim 1 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 18, the claim is anticipated by claim 1 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Per dependent claim 20, the claim is anticipated by claim 2 of U.S. Patent 12153515 but the mapping is omitted for the sake of brevity.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6, 9, 11-13 and 16-18 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Gunda et al. [Pub.No.: US 20210064280 A1] (hereinafter “Gunda”).
Independent Claims:
Per independent claim 1, Gunda teaches:
A method comprising:
generating mapping information in which, for each frame of a plurality of frames stored in a storage component, at least one logical address is assigned to the frame (see entire paragraph [0029], mapping table 120 associating each video frame with a logical address; see paragraph [0028], the video frames are stored in NVM 110); and
providing a batch read request to the storage component, to read all of the at least one logical address assigned to the frame by referring the mapping information (see entire paragraph [0032], sending a read command specifying one or more logical addresses associated with the frames, the mapping table 120 is accessed to translate the logical addresses specified in the read command. Note that this read command can be construed as a batch read request as it specifies one or more logical addresses. Furthermore, under the broadest reasonable interpretation of the instant claim, even if this read command specifics only one logical address associated with a particular frame, it may still be construed as a batch read request that reads only one LBA that is allocated to a particular frame).
Per independent claim 13, Gunda teaches:
A system (see Fig. 1 and paragraph [0022], lines 1-5, system 100 that is formed by host 104 and storage device 102) comprising:
a storage component configured to store image frames (see Fig. 1 and paragraph [0028], storage device 102, which comprises NVM 110 that stores the video frames. Also note that video frames are still image frames, see paragraph [0020], lines 4-5); and
a processing component (see Fig. 1, host 104) configured to obtain one image frame of the image frames from the storage component (see paragraph [0032], host 104 retrieves video frame data from storage device 102),
wherein the processing component provides a batch read request to the storage component to read all logical addresses assigned to the one image frame (see entire paragraph [0032], sending a read command specifying one or more logical addresses associated with the frame. Note that this read command can be construed as a batch read request as it specifies one or more logical addresses. Furthermore, under the broadest reasonable interpretation of the instant claim, even if this read command specifics only one logical address associated with a particular frame, it may still be construed as a batch read request that reads only one LBA that is allocated to a particular frame. Also note that dependent claim 16 of the instant application clarifies that at least one logical address is assigned to the image frame, indicating a case where only one logical address is assigned to a particular frame).
Dependent Claims:
Per claim 6, Gunda further teaches numbers of the at least one logical address assigned to at least a portion of the plurality of frames are different from each other (see Fig. 2 and 3, each video frame is assigned a different number as its associated logical address, the examples shown being 0, 1 and 50. Also see paragraph [0044], lines 14-20, Gunda teaches main frames and smaller sized sub frames, indicating video frames of different sizes and hence different numbers of assigned logical addresses).
Per claim 9, Gunda further teaches the mapping information is generated when the plurality of frames is stored in the storage component (see Gunda, paragraph [0018] for encoding and writing video frames to a storage device, and paragraph [0029] for mapping each frame. As such Gunda generates the mapping for each frame when it is first/initially encoded and written).
Per claim 11, Gunda further teaches the at least one logical address is at least one logical block address (LBA) (see paragraph [0029], lines 12-24 for LBA).
Per claim 12, Gunda further teaches the each of the plurality of frames includes at least one of an intra frame, a bidirectional frame or a predicted frame (paragraph [0110] of instant application’s specification defines an intra frame as a frame including all pieces of data of one frame, as such each of Gunda’s video frames can be viewed as an intra frame as each of them includes all pieces of data of one frame).
Per claim 16, Gunda further teaches the processing component generates the batch read request by referring a mapping table in which, for each image frame of the image frames, at least one logical address is assigned to the image frame (see entire paragraph [0029], mapping table 120 associating each video frame with a logical address).
Per claim 17, Gunda further teaches the mapping table includes, for each image frame of the image frames, a mapping of the at least one logical address to a frame number assigned to the image frame (see entire paragraph [0029] and Figs. 2-3, mapping table 120 associates video frame numbers with logical addresses by mapping video frame 2 to logical address 1, and video frame 51 to logical address 50).
Per claim 18, Gunda further teaches the storage component performs a read operation on a memory area corresponding to at least one logical address in response to the batch read request (see Figs. 2-3 and paragraph [0032], frames are associated with logical addresses mapped to physical memory addresses, from where the frame are read).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 10, 14-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gunda, and further in view of Walker et al. [Pub.No.: US 20220116660 A1] (hereinafter “Gunda”).
Independent Claim:
Per independent claim 19, Gunda teaches:
A method, comprising:
providing a batch read request (see entire paragraph [0032], sending a read command specifying one or more logical addresses associated with the frame. Note that this read command can be construed as a batch read request as it specifies one or more logical addresses. Furthermore, under the broadest reasonable interpretation of the instant claim, even if this read command specifics only one logical address associated with a particular frame, it may still be construed as a batch read request that reads only one LBA that is allocated to a particular frame. Also note that dependent claim 20 of the instant application clarifies that at least one logical address is assigned to each image frame, indicating a case where only one logical address is assigned to a particular frame) to a storage component that stores image frames (see Fig. 1 and paragraph [0028], storage device 102, which comprises NVM 110 that stores the video frames. Also note that video frames are still image frames, see paragraph [0020], lines 4-5), to read all logical addresses assigned to one image frame of the image frames (see entire paragraph [0032], sending a read command specifying one or more logical addresses associated with the frame. Also note that dependent claim 20 of the instant application clarifies that at least one logical address is assigned to each image frame, indicating a case where only one logical address is assigned to a particular frame);
obtaining the one image frame from the storage component (see paragraph [0032], reading the frame from storage device 102).
Gunda does not specifically teaches:
resizing the obtained image frame; and
storing the resized image frame to the storage component.
Walker teaches an analogous method wherein video frames are scaled/resized so that the frames may be rendered and effectively displayed at a higher resolution and/or frame rate (see Walker, entire paragraphs [0002], [0006], [0028], [0030] and [0033]). Because Gunda teaches a method for analyzing and displaying video frames to identify CCTV footages of an incident such as a warehouse or traffic accident (see Gunda, entire paragraphs [0004] and [0019]-[0021]), it would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to apply Walker’s scaling/resizing techniques to improve the resolution and/or frame rate of Gunda’s video frames in order to display the recorded incidents more effectively. Furthermore, as Gunda teaches the video frames are stored in non-volatile memory for future playback (see Gunda, paragraphs [0004]), it would have been also obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to store the resized/scaled video frames in Gunda’s NVM 110 for future replay and/or analysis. As such, the combined teachings of Gunda and Walker render obvious the limitations of “resizing the obtained image frame; and storing the resized image frame to the storage component”.
Dependent Claims:
Per claim 2, Gunda in view of Walker further teaches (the reason for combining Gunda and Walker for the instant claim is already set forth above in the rejection of claim 19 and will not be repeated here):
performing a scaling operation for each frame of the plurality of frames, the scaling operation including (see Walker, entire paragraphs [0002], [0006], [0028], [0030] and [0033] for scaling operations):
obtaining whole data included in the frame based on the batch read request (see Gunda entire paragraph [0032] and rejection of claim 1 set forth above for batch reading the video frame),
decoding the frame to generate a decoded frame (Walker teaches decoding frame in paragraphs [0028] and Fig. 2, and Gunda teaches the video frames are encoded in paragraph [0018], as such there is a need to apply Walker’s decoding technique to Gunda’s encoded video frames so that they can be resized/scaled; also note that Walker’s decoder 202 transmits decoded frames to its scaler 204 which performs the scaling/resizing operations), and resizing the decoded frame to generate a resized frame (see rejection of claim 19 set forth above for resizing video frames),
encoding the resized frame to generate an encoded frame (Walker teaches encoding the resized frame for display in Fig. 2 and paragraph [0033]; also note that Gunda teaches the video frames are stored as encoded video frames in paragraph [0018], as such the resized frames should be encoded in the combined teachings of Gunda and Walker), and
providing a write request to write the encoded frame to the storage component (see rejection of claim 19 set forth above for similar limitation’s statement of rejection).
Per claim 3, Gunda in view of Walker further teaches:
resizing the decoded frame includes changing a resolution of the decoded frame (see Walker, paragraph [0030], scaling frame resolution).
Per claim 4, Gunda in view of Walker further teaches:
resizing the decoded frame includes changing a frame rate of the decoded frame (see Walker, paragraph [0030], scaling video frame rate).
Per claim 5, Gunda in view of Walker further teaches:
the batch read request is provided in an idle state in which the decoding and the encoding are not performed (based on teachings of claim 2 which is dependent on by the instant claim, the decoding and encoding steps are performed after the obtaining step. As batch read request is issued to perform the obtaining step, it would be a logical conclusion that the batch read request when the decoding and encoding are not performed. In the combined teachings of Gunda and Walker and as set forth above in the rejection of claim 2, Gunda’s batch read occurs prior to the decoding and encoding steps shown in the Fig. 2 of Walker).
Per claim 10, Gunda in view of Walker further teaches:
the mapping information is generated when each frame of the plurality of frame is first encoded (see Gunda, paragraph [0018] for encoding and writing video frames to a storage device, and paragraph [0029] for mapping each frame. As such Gunda generates the mapping for each frame when it is first/initially encoded and written).
Per claim 14, Gunda in view of Walker further teaches:
the processing component resizes the obtain image frame (see rejection of claim 19 set forth above for similar limitation’s statement of rejection).
Per claim 15, Gunda in view of Walker further teaches:
the processing component stores the resized image frame to the storage component (see rejection of claim 19 set forth above for similar limitation’s statement of rejection).
Per claim 20, Gunda in view of Walker further teaches:
referring to a mapping table in which, for each image frame of the image of frames, at least one logical address is assigned to the image frame (see Gunda, entire paragraph [0029], mapping table 120 associating each video frame with a logical address).
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter (the crossed out portions are limitations not taught or rendered obvious by the cited prior art references):
Per claim 7, Gunda further teaches:
providing a read request to the storage component for one logical address (see Gunda, paragraph [0032] for accessing logical addresses to retrieve video frames),
obtaining a piece of data corresponding to the one logical address from the storage component (see Ibid.),
determining whether all pieces of data for encoding the frame have been obtained, based on at least one piece of data obtained from the storage component (see Gunda, paragraph [0032] and Figs. 2-3, the length field indicates how much data is read for a particular logical address, and this determination must be made to ensure the complete and correct reading of a video frame, also note that Gunda’s video frames are encoded, see Gunda, paragraph [0018] for encoding and writing video frames to a storage device), and
generating the mapping information of the frame (see entire paragraph [0029], mapping table 120 associating each video frame with a logical address) when the all the pieces of data for encoding the frame have been obtained (Gunda’s video frames are encoded, see Gunda, paragraph [0018] for encoding and writing video frames to a storage device, and the mapping of the frame to the associated logical address is generated when the frame is being written).
However, Gunda fails to teach or render obvious that each of the above steps are performed as a part of generating the mapping information as claimed (the instant application’s specification teaches generating a mapping table using the scaler 310 in paragraphs [0058]-[0068] by performing the above claimed steps). Gunda’s mapping table 120 is a data structure stored in Gunda’s NVM 110, but it is not generated by reading a piece of data corresponding to one logical address, determining whether all pieces of pieces of data for encoding a frame have been read based on the piece of data already read, and generated when all pieces of data for encoding the frame have been read.
Per claim 8, the claim is dependent on claim 7 and as such is allowable for at least the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN X GU whose telephone number is (571)272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
20 December 2025