Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-27 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0166429 to Lee et al. (“Lee”).
With respect to claim 11, Lee discloses in Figs. 10-11 an integrated circuit, comprising:
a multiplexer (e.g., 600), including:
an input (e.g., VIN1);
an output (e.g., OUT);
a main transistor (e.g., S1) having a source terminal coupled to the input, a drain terminal coupled to the output (e.g., OUT), and a gate terminal;
a first bootstrap circuit (e.g., 610 and 6201) coupled to the input (e.g., VIN1). Figs. 10-11 fail to explicitly disclose that the shared charging circuit 610 may be duplicated and provided for each corresponding boosting circuit 6201-6201n). However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that a shared circuit may be duplicated and provided for each sharing circuit; an official notice of the foregoing fact is hereby taken. For example, Figs. 4-5 of Lee (US 2022/0166429) discloses that charging circuit including a capacitor and switches to charge a capacitor for boosting an output voltage may be duplicated for each boosting circuit as per Para. 40. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to duplicate and provide the shared charging circuit 610 to each boosting circuit 6201-6201n in Figs. 10-11 of Lee in light of the notoriously well-known method of duplicating and providing a shared circuit to each sharing circuit because such a modification provides the same charging function and allows spread use when the space occupied by the charging circuit is not an issue.
With respect to claim 12, the first bootstrap circuit (e.g., 610) includes: a first pair of transistors (e.g., SC2 and SB21 may be implemented by MOS transistors as per Para. 44); a first bootstrap capacitor (e.g., CB); and a second pair of transistors (e.g., SC1 and SB11 may be implemented by MOS transistors as per Para. 44)).
With respect to claim 13, the first bootstrap capacitor (e.g., CB) is coupled between the first pair of transistors (e.g., SC2 and SB21) and the second pair of transistors (e.g., SC1 and SB11).
With respect to claims 14-16, the second bootstrap circuit (e.g., 610 duplicated and provided for 620n) includes: a third pair of transistors; a second bootstrap capacitor; and a fourth pair of transistors (e.g., see claim 13 discussion) and the second bootstrap capacitor is coupled between the third pair of transistors and the fourth pair of transistors (e.g., see claim 13 discussion).
With respect to claim 17, the main transistor (e.g., S1) includes a field effect transistor; alternatively, use of a field effect transistor for a switch was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention and as such, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a field effect transistor for the switch S1 in Figs. 10-11.
With respect to claim 18, the main transistor (e.g., S1) is configured to have a substantially constant resistance during operation (e.g., when a boosted voltage applied to the gate of S1 is constant for a duration, however small, the resistance of S1 in response is constant).
With respect to claim 19, the first bootstrap circuit (e.g., 610 and 6201) includes a phase generation circuit configured to: produce a phase signal (e.g., the phase of the gate signal to S1 to selectively decouple a bootstrap capacitor (e.g., C8) of the first bootstrap circuit from the input (e.g., VIN1)) to selectively decouple a bootstrap capacitor of the first bootstrap circuit from the input.
With respect to claim 20, a phase generation circuit (e.g., the control circuit that generates the switch signals for 610 and 620) is also disclosed.
With respect to claim 21, the above discussion for claim 11 similarly applies.
With respect to claims 22-27, the above discussion for dependent claims of claim 11 similarly applies. Further, for claims 26-27, a second switch (e.g., Sn) is coupled between the output terminal (e.g., OUT) and a second input terminal (e.g., VINn).
With respect to claim 8, the above discussion for claims 11 and 14-16 similarly applies.
With respect to claim 9, Figs. 4-5 disclose an analog to digital converter (e.g., 320).
With respect to claim 10, Fig. 9 discloses first and second clock signals out of phase by 180 degrees and used by the Figs. 10-11 circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2836
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