DETAILED ACTION
Response to Arguments
Applicants’ arguments filed 06/15/26 have been fully considered but they are not
persuasive.
Applicants argue against references (Hwang, Lin, and Nguyen) individually.
The Examiner respectfully disagrees and in response, to applicants’ arguments against the references individually, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Hwang teaches a flash memory controller comprising: an encoder circuit, for performing a local encoding operation upon a data unit to be written into a portion of a page unit of the flash memory device and performing a global encoding operation upon multiple data units to be written into the page unit according to a coding matrix so as to generate and write error correction code data into the page unit (see col. 1, lines 63-67 to col. 2, lines 1-15 and 3, lines 42-59, col. 4, lines 47-67 to col. 5, lines 1-12, col. 15, lines 22-33) and a decoder circuit, for performing a local decoding operation upon the data unit read from the portion of the page unit and performing a global decoding operation upon the multiple data units read from the page unit according to the error correction code data corresponding to the coding matrix to obtain correct data of the page unit and a processing circuit, coupled to the encoder circuit and the decoder circuit, for dynamically determining the coding matrix to dynamically select a coding mode (see col. 5, lines 13-64, col. 15, lines 34-48, col. 3, lines 36-41, col. 4, lines 19-31). Lin further teaches performing a local and global encoding and decoding operation (see col. 10, lines 4-62, and col. 14, lines 60-67 to col. 15, lines 1-11). Furthermore, Nguyen, teaches dynamically determining a coding matrix to dynamically select a coding mode; wherein the processing circuit dynamically determines the coding matrix in response to a page size of the page unit (see par. [0025]) and further paragraph [0067] teaches “at operation 320, code and generate the processing logic may encode the received host data using a dynamically configured LDPC encoded data therefrom (e.g., one or more codewords therefrom). In at least one embodiment, for example, the processing logic may provide an LDPC encoder with a sequence of one or more symbols of data and instruct the LDPC encoder to generate an encoded codeword therefrom. In at least one embodiment, for example, the processing logic may use the LDPC encoder to process K bits of host data at a time to generate codewords of length N therefrom, which may contain K bits of host data and N-K (or M) bits of redundancy data (or parity-check bits). In at least one embodiment, for example, the LDPC encoder may use a parity-check matrix that defines an LDPC code to process a sequence of host data. By way of example, with reference to FIG. 2, a binary LDPC code may be defined by a parity-check matrix H of size M×N, which the LDPC encoder may use to process K bits (or N-M bits) of host data to generate a codeword C of length N. In at least one embodiment, a size of parity matrix H and/or value of K may be chosen so that the resulting codeword C is a particular size. The size of parity matrix H and/or value of K, for example, may be selected such that the codeword C generated therefrom is the same size as a page or block (or other grouping) of memory cells, which may facilitate storage of the encoded data on a memory device.
In addition to that, for example, the reference (Nguyen) is not required to teach the exact claim language (i.e., dynamically determines the coding matrix in response to a page size of the page unit) to that of the present invention since the concept is taught to the extent required by the actual claim language. Therefore, the applied references have been applied appropriately, and the 103 rejection is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
correction of the statutory basis for the rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be
the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102 of this title, if the
differences between the claimed invention and the prior art are such that the claimed
invention as a whole would have been obvious before the effective filing date of the
claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains. Patentability shall not be negated by the manner in which the
invention was made.
Claims 1-2, 9-13, 19-20 are rejected under 35 U.S.C. 103(a) as being unpatentable
over (U.S. PN: Hwang et al. "herein Hwang" (U.S. PN:11,562,803) in view of Lin et
al. "herein as Lin" (U.S. PN: 11,430,538) and further in view of Nguyen et al.
"herein Nguyen" (20240330105).
As per claim 1:
Hwang substantially teaches a flash memory controller, to be coupled between a host
device and a flash memory device (see col. 1, lines 63-67 to col. 2, lines 1-15 and 3, lines 42-59),
comprising: an encoder circuit, for performing a local encoding operation upon a data unit to be
written into a portion of a page unit of the flash memory device and performing a global
encoding operation upon multiple data units to be written into the page unit according to a
coding matrix so as to generate and write error correction code data into the page unit (see col. 4,
lines 47-67 to col. 5, lines 1-12, col. 15, lines 22-33) a decoder circuit, for performing a local
decoding operation upon the data unit read from the portion of the page unit and performing a
global decoding operation upon the multiple data units read from the page unit according to the
error correction code data corresponding to the coding matrix to obtain correct data of the page
unit (see col. 5, lines 13-64, col. 15, lines 34-48) and a processing circuit, coupled to the encoder
circuit and the decoder circuit, for dynamically determining the coding matrix to dynamically
select a coding mode (see col. 3, lines 36-41, col. 4, lines 19-31).
Huang substantially teaches the claimed invention described in claim 1 (as indicated
above). However, Huang does not explicitly teach and performing a local and global encoding
and decoding operation. Lin, in an analogous art, teaches performing a local and global encoding
and decoding operation (see col. 10, lines 4-62, and col. 14, lines 60-67 to col. 15, lines 1-11).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the invention to modify Huang with the teachings of Lin by performing a
local and global encoding and decoding operation.
This modification would have been obvious to one of ordinary skill in the art, before the
effective filing date of the invention because one of ordinary skill in the art would have
recognized that performing a local and global encoding and decoding operation would have
improved security and increased capacity.
Neither Huang nor Lin explicitly discloses dynamically determining a coding matrix to dynamically select a coding mode; wherein the processing circuit dynamically determines the coding matrix in response to a page size of the page unit. Nguyen, in an analogous art, teaches dynamically determining a coding matrix to dynamically select a coding mode; wherein the processing circuit dynamically determines the coding matrix in response to a page size of the page unit (see par. [0025]) and further paragraph [see 0067] teaches “at operation 320, code and generate the processing logic may encode the received host data using a dynamically configured LDPC encoded data therefrom (e.g., one or more codewords therefrom). In at least one embodiment, for example, the processing logic may provide an LDPC encoder with a sequence of one or more symbols of data and instruct the LDPC encoder to generate an encoded codeword therefrom. In at least one embodiment, for example, the processing logic may use the LDPC encoder to process K bits of host data at a time to generate codewords of length N therefrom, which may contain K bits of host data and N-K (or M) bits of redundancy data (or parity-check bits). In at least one embodiment, for example, the LDPC encoder may use a parity-check matrix that defines an LDPC code to process a sequence of host data. By way of example, with reference to FIG. 2, a binary LDPC code may be defined by a parity-check matrix H of size M×N, which the LDPC encoder may use to process K bits (or N-M bits) of host data to generate a codeword C of length N. In at least one embodiment, a size of parity matrix H and/or value of K may be chosen so that the resulting codeword C is a particular size. The size of parity matrix H and/or value of K, for example, may be selected such that the codeword C generated therefrom is the same size as a page or block (or other grouping) of memory cells, which may facilitate storage of the encoded data on a memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to dynamically determine a coding matrix to dynamically select a coding mode to modify Huang with the teachings of Nguyen by dynamically determining a coding matrix to dynamically select a coding mode. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention at the time the invention was made, because one of ordinary skill in the art would have recognized that by determining dynamically a coding matrix to dynamically select a coding; wherein the processing circuit dynamically determines the coding matrix in response to a page size of the page unit mode would facilitate utilization of flexible and efficient memory configurations.
As per claim 3:
The combination of Huang, Lin, and Nguyen in the above rejection teach performing the
local encoding operation upon the data unit to be written into the portion of the page unit of the
flash memory device according to a basic parity check matrix of the coding matrix to generate a
parity data; and a raptor encoder, coupled to the parity encoder, for performing the global
encoding operation upon the multiple data units, to be written into the page unit, and multiple
parity data of the multiple data units according to a raptor matrix of the coding matrix to generate
a raptor parity data (see col. 10, lines 34-62 in Lin)
As per claim 9:
The combination of Huang, Lin, and Nguyen in the above rejection teach wherein the
decoder circuit comprises: a parity decoder, for performing the local decoding operation upon the
data unit read from the portion of the page unit of the flash memory device according to the
parity data read from the page unit; and a raptor decoder, coupled to the parity decoder, for
performing the global encoding operation upon the multiple data units and the multiple parity
data read from the page unit according to the raptor parity data read from the page unit (see col.
11, lines 20-46 in Lin).
As per claim 10:
The combination of Huang, Lin, and Nguyen in the above rejection teach wherein the
decoder circuit is arranged to perform the global decoding operation after a result of the local
decoding operation is not successful (see col. 11, lines 20-46 in Lin).
Claim 11, this claim is directed to a method is rejected for the same reasons as in claim 1.
Claim 13, this claim is directed to a method is rejected for the same reasons as in claim 3.
Claim 19, this claim is directed to a method is rejected for the same reasons as in claim 9.
Claim 20, this claim is directed to a method is rejected for the same reasons as in claim 10.
Allowable subject matter
Claims 4-8, 14-18 are objected to as being dependent upon a rejected base claim
but would be allowable if rewritten independent from including all of the limitation
of the base claim and any intervening claims.
Below are Examiner's reasons for indication of allowable subject matter:
As per claims 4 and 14:
The claimed invention comprises wherein when the processing circuit selects a first
coding mode corresponding to a data length of a data unit, the encoder circuit performs an
encoding operation upon the data unit to generate a corresponding parity data and performs
another encoding operation upon the data unit and the corresponding parity data to generate a
raptor parity data, when the processing circuit selects a second coding mode corresponding to a
data length of two data units, the encoder circuit performs the encoding operation respectively
upon the two data units to generate two corresponding parity data and perform the another
encoding operation upon the two data unit and the two corresponding parity data to generate the
raptor parity data: and, when the processing circuit selects a third coding mode corresponding to
The data length of four data units, the encoder circuit performs the encoding operation respectively upon the four data units to generate four corresponding parity data and perform another encoding operation upon the four data unit and the four corresponding parity data to generate the raptor parity data which the prior art do not teach or render obvious.
As per claims 5 and 15:
The claimed invention comprises wherein when the processing circuit selects a multi-
coding mode corresponding to a data length of a data unit and a data length of four data units, the
encoder circuit performs a first encoding operation upon the data unit to generate a
corresponding parity data and performs a second encoding operation upon the data unit and the
corresponding parity data to generate a local raptor parity data; and, the encoder circuit performs
a third encoding operation upon the four data units, four corresponding parity data, and four local
raptor parity data to generate a global raptor parity data which the prior art do not teach or render
obvious.
As per claims 6 and 16:
The claimed invention comprises wherein the coding matrix comprises: a first sub-matrix
part, arranged in 4xm rows and 4xn columns, comprising four basic parity check matrix units
arranged in a diagonal line from a top-left corner of the first sub-matrix part to a bottom-right
corner of the first sub-matrix part, a basic parity check matrix unit being arranged in m rows and
n columns; a second sub-matrix part comprising at least one raptor matrix which is formed by
four basic raptor matrix units each being arranged in one row and n columns; a third sub-matrix
part comprising an identify matrix; and a fourth sub-matrix part being a zero matrix; wherein the
first sub-matrix part is disposed at a top-left position of the coding matrix, the second sub-matrix
part is disposed at a bottom-left position of the coding matrix, the third sub-matrix part is
disposed at a bottom-right position of the coding matrix, and the fourth sub-matrix part is
disposed at a top-right position of the coding matrix which the prior art do not teach or render
obvious.
As per claims 7 and 17:
The claimed invention comprises wherein the coding matrix comprises: a first sub-matrix
part, arranged in 4xm rows and 4xn columns, comprising four basic parity check matrix units
arranged in a diagonal line from a top-left corner of the first sub-matrix part to a bottom-right
corner of the first sub-matrix part, a basic parity check matrix unit being arranged in m rows and
n columns; a second sub-matrix part comprising two raptor matrix units in which a first raptor
matrix unit is a matrix arranged in one-row and 4xn columns and disposed at a top position of
the second sub-matrix part while a second raptor matrix unit is a different matrix arranged in
one-row and 4xn columns and disposed at a bottom position of the second sub-matrix part; a
third sub-matrix part comprising an identify matrix arranged in two rows and two columns; and a
fourth sub-matrix part being a zero matrix arranged in 4xm rows and two columns; wherein the
first sub-matrix part is disposed at a top-left position of the coding matrix, the second sub-matrix
part is disposed at a bottom-left position of the coding matrix, the third sub-matrix part is
disposed at a bottom-right position of the coding matrix, and the fourth sub-matrix part is
disposed at a top-right position of the coding matrix which the prior art do not teach or render
obvious.
As per claims 8 and 18:
The claimed invention comprises wherein the coding matrix comprises: a first sub-matrix
part, arranged in 4xm rows and 4xn columns, comprising four basic parity check matrix units
arranged in a diagonal line from a top-left corner of the first sub-matrix part to a bottom-right
corner of the first sub-matrix part, a basic parity check matrix unit being arranged in m rows and
n columns; a second sub-matrix part comprising two raptor matrix units in which a first raptor
matrix unit is a matrix arranged in four rows and 4xn columns and disposed at a top position of
the second sub-matrix part while a second raptor matrix unit is a different matrix arranged in
one-row and 4xn columns and disposed at a bottom position of the second sub-matrix part, the
first raptor matrix unit comprising four basic raptor matrix units arranged in a diagonal line from
a top-left corner of the first raptor matrix unit to a bottom-right corner of the first raptor matrix
unit: a third sub-matrix part comprising an identify matrix arranged in five rows and five
columns: and a fourth sub-matrix part being a zero-matrix arranged in 4xm rows and five
columns: wherein the first sub-matrix part is disposed at a top-left position of the coding matrix,
The second sub-matrix part is disposed at a bottom-left position of the coding matrix, the third
sub-matrix part is disposed at a bottom-right position of the coding matrix, and the fourth sub-
matrix part is disposed at a top-right position of the coding matrix which the prior art do not
teach or render obvious.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAW T ABRAHAM whose telephone number is (571)272-3812. The examiner can normally be reached on 8AM-4:30PM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phonenumber for the organization where this application or proceeding is assigned is(703) 872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
Prosecution Insights